scholarly journals Concurrent Models of Flash Memory Device Behaviour

2009 ◽  
pp. 70-83 ◽  
Author(s):  
Andrew Butterfield ◽  
Art Ó Catháin
Keyword(s):  
Flash Memory ◽  
Memory Device

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Enhanced Programming and Erasing Speeds in P-Channel Charge-Trapping Flash Memory Device With SiGe Buried Channel

2012 ◽  
Vol 33 (9) ◽  
pp. 1264-1266 ◽  
Author(s):  
Li-Jung Liu ◽  
Kuei-Shu Chang-Liao ◽  
Yi-Chuen Jian ◽  
Jen-Wei Cheng ◽  
Tien-Ko Wang ◽  
...  
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Buried Channel

Study for aluminum metal patterning process with oxide hard mask in 90-nm s-flash memory device fabrication

2008 ◽  
Author(s):  
Sang Il Hwang ◽  
Ki Jun Yun ◽  
Sang Wook Ryu ◽  
Kang Hyun Lee ◽  
Jae Won Han
Keyword(s):  
Flash Memory ◽  
Memory Device ◽  
Device Fabrication ◽  
Hard Mask ◽  
Aluminum Metal

scholarly journals Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory

Nanomaterials ◽  
2018 ◽  
Vol 8 (10) ◽  
pp. 799 ◽  
Author(s):  
Jer Wang ◽  
Chyuan Kao ◽  
Chien Wu ◽  
Chun Lin ◽  
Chih Lin
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Dielectric Constants ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Hysteresis Curve ◽  
Band Shift ◽  
K Value ◽  
High K

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.

scholarly journals Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device

2016 ◽  
Vol 2016 ◽  
pp. 1-6 ◽  
Author(s):  
W. J. Liu ◽  
L. Chen ◽  
P. Zhou ◽  
Q. Q. Sun ◽  
H. L. Lu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Room Temperature ◽  
Metal Layer ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Memory Device ◽  
Water Molecules ◽  
Oh Groups ◽  
Chemical Vapor Deposited ◽  
A Charge

We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.

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