Characteristics of thin gate dielectric in a rapid thermal processing machine and temperature uniformity studies

1988 ◽  
Vol 47 (3) ◽  
pp. 237-247 ◽  
Author(s):  
N. Chan Tung ◽  
Y. Caratini ◽  
C. D'Anterroches ◽  
J. L. Buevoz
Keyword(s):  
Thermal Processing ◽  
Gate Dielectric ◽  
Rapid Thermal Processing ◽  
Temperature Uniformity ◽  
Processing Machine

Monte Carlo Thermal Model of an Integrating Light Pipe for Rapid Thermal Processing

1996 ◽  
Vol 429 ◽  
Author(s):  
J. C. Thomas ◽  
D. P. Dewitt
Keyword(s):  
Monte Carlo ◽  
Thermal Processing ◽  
Monte Carlo Model ◽  
Rapid Thermal Processing ◽  
Width Ratio ◽  
Temperature Uniformity ◽  
System Parameters ◽  
Light Pipe ◽  
End Wall ◽  
Cavity Width

AbstractA Monte Carlo model is developed to simulate transient wafer heating as a function of system parameters in a kaleidoscope- or integrating light-pipe type cavity with square cross-section. Trends in wafer temperature uniformity are examined as a function of length-to-width ratio, cavity width, and the number of heating lamps. The effect on temperature determination by a radiometer placed in the bottom end wall of the cavity is simulated.

Optimization of Process Parameter and Temperature Uniformity On Wafers For Rapid Thermal Processing

1995 ◽  
Vol 387 ◽  
Author(s):  
Andreas Tillmann
Keyword(s):  
Standard Deviation ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Simulation Software ◽  
Process Parameter ◽  
Parameter Distribution ◽  
Temperature Uniformity ◽  
New Strategy ◽  
The Impact

AbstractA new strategy based algorithm to optimize process parameter uniformity (e.g.sheet resistance, oxide thickness) and temperature uniformity on wafers in a commercially available Rapid Thermal Processing (RTP) system with independent lamp control is described. The computational algorithm uses an effective strategy to minimize the standard deviation of the considered parameter distribution. It is based on simulation software which is able to calculate the temperature and resulting parameter distribution on the wafer for a given lamp correction table. A cyclical variation of the correction values of all lamps is done while minimizing the standard deviation of the considered process parameter. After the input of experimentally obtained wafer maps the optimization can be done within a few minutes. This technique is an effective tool for the process engineer to use to quickly optimize the homogeneity of the RTP tool for particular process requirements. The methodology will be shown on the basis of three typical RTP applications (Rapid Thermal Oxidation, Titanium Silicidation and Implant Annealing). The impact of variations of correction values for single lamps on the resulting process uniformity for different applications will be discussed.

Rapid Thermal Processes for Future Nanometer MOS Devices

1998 ◽  
Vol 525 ◽  
Author(s):  
John R. Hauser
Keyword(s):  
Thermal Processing ◽  
Gate Dielectric ◽  
Rapid Thermal Processing ◽  
Dielectric Materials ◽  
Nanometer Scale ◽  
Thermal Processes ◽  
Contact Material ◽  
Mos Devices ◽  
Front End ◽  
Projected Changes

ABSTRACTScaling of MOS devices is projected to continue down to device dimensions of at least 50 nm. However, there are many potential roadblocks to achieving such dimensions and many standard materials and front-end processes which must be significantly changed to achieve these goals. The most important areas for change include (a) gate dielectric materials, (b) gate contact material, (c) source/drain contacting structure and (d) fundamental bulk CMOS structure. These projected changes are reviewed along with possible applications of rapid thermal processing to achieving future nanometer scale MOS devices.

Simulation of Temperature Effects during Rapid Thermal Processing

1989 ◽  
Vol 146 ◽  
Author(s):  
R. Kakoschek ◽  
E. BuβMann
Keyword(s):  
Stationary State ◽  
Excellent Agreement ◽  
Thermal Processing ◽  
Temperature Effects ◽  
Rapid Thermal Processing ◽  
Nonuniform Heating ◽  
Temperature Uniformity ◽  
Nonuniform Illumination ◽  
Potential Sources ◽  
Wafer Edge

ABSTRACTA complete theory of wafer heating during rapid thermal processing (RTP) is presented. Excellent agreement with experimental results of two commercial RTP systems is obtained. The temperature uniformity is limited by radiation loss at the wafer edge in the stationary state and by nonuniform illumination of the wafer during ramp-up. Structures on wafers are also potential sources for nonuniform heating. Considerable dynamic temperature inhomogeneities during rap-up might limitfu ture applications of RTPe specially when wafer sizes become larger. Possible improvements are suggested regarding adequate process cycling, chip and equipment design.

SIMS STUDY OF SILICON OXYNITRIDE RAPID THERMALLY GROWN IN NITRIC OXIDE

2001 ◽  
Vol 08 (05) ◽  
pp. 569-573
Author(s):  
R. LIU ◽  
K. H. KOA ◽  
A. T. S. WEE ◽  
W. H. LAI ◽  
M. F. LI ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Depth Distribution ◽  
Secondary Ion Mass Spectrometry ◽  
Gate Dielectric ◽  
State Of The Art ◽  
Rapid Thermal Processing ◽  
Growth Characteristics ◽  
Silicon Oxynitride ◽  
Mos Devices ◽  
Secondary Ion

As the gate dielectric for ULSI MOS devices scales in the ultrathin regime, it is fabricated increasingly with silicon oxynitride instead of silicon dioxide films. One way to obtain silicon oxynitride films is the rapid thermal oxidation of silicon in NO (RTNO). Earlier RTNO growth studies were not sufficiently comprehensive as well as limited by temperature uncertainty and nonuniformity across the wafer. Using a state-of-the-art rapid thermal processing (RTP) system, RTNO growth characteristics at oxidation pressures of 100 and 760 Torr, oxidation temperatures from 900 to 1200°C and oxidation times from 0 to 480 s were obtained and investigated. Anomalies in the growth characteristics were observed. It was also demonstrated that secondary ion mass spectrometry (SIMS) using the MCs + method could be used to accurately determine the depth distribution of N in ultrathin silicon oxynitride films.

Modelling of Temperature Distribution of Semiconductors During Rapid Thermal Processing

1994 ◽  
Vol 342 ◽  
Author(s):  
Andreas Tillmann
Keyword(s):  
Temperature Distribution ◽  
Material Property ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Two Dimensional ◽  
Temperature Uniformity ◽  
Temperature Dependent ◽  
Incident Intensity ◽  
Circular Test ◽  
Contour Plots

ABSTRACTThe modelling of temperature distribution on semiconductor wafers in common RTP-equipment is described. The incident intensity distribution on the wafer is calculated using raytracing. Based on this distribution the temperature distribution on the wafer is determined solving the two-dimensional heat conduction equation. If the dependence of a considered material property on the process temperature is known, the calculated temperature distribution can be convened to a distribution of this parameter.The distinctive feature of the described algorithms is the two-dimensional treatment of the distributions using a grid of ring segments, each with equal area. This grid is identical to the usual circular test patterns of multipoint measurement equipment. This is convenient since the evaluation of temperature uniformity in RTP equipment is done mostly by mapping an appropriate temperature dependent material property. All calculated distributions can be presented by contour plots as well as 3-D plots. This results in a very suitable method to compare simulated and experimental wafer maps.The agreement between simulated and experimental temperature distributions is shown.

Optimization of Process Parameter and Temperature Uniformity on Wafers for Rapid Thermal Processing

1995 ◽  
Vol 389 ◽  
Author(s):  
Andreas Tillmann
Keyword(s):  
Standard Deviation ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Simulation Software ◽  
Process Parameter ◽  
Parameter Distribution ◽  
Temperature Uniformity ◽  
New Strategy ◽  
The Impact

ABSTRACTA new strategy based algorithm to optimize process parameter uniformity (e.g. sheet resistance, oxide thickness) and temperature uniformity on wafers in a commercially available Rapid Thermal Processing (RTP) system with independent lamp control is described. The computational algorithm uses an effective strategy to minimize the standard deviation of the considered parameter distribution. It is based on simulation software which is able to calculate the temperature and resulting parameter distribution on the wafer for a given lamp correction table. A cyclical variation of the correction values of all lamps is done while minimizing the standard deviation of the considered process parameter. After the input of experimentally obtained wafer maps the optimization can be done within a few minutes. This technique is an effective tool for the process engineer to use to quickly optimize the homogeneity of the RTP tool for particular process requirements. The methodology will be shown on the basis of three typical RTP applications (Rapid Thermal Oxidation, Titanium Silicidation and Implant Annealing). The impact of variations of correction values for single lamps on the resulting process uniformity for different applications will be discussed.

Silicon Oxynitride and Oxide-Nitride-Oxide Gate Dielectrics by Combined Plasma-Rapid Thermal Processing

1994 ◽  
Vol 342 ◽  
Author(s):  
Y. Ma ◽  
S.V. Hattangady ◽  
T. Yasuda ◽  
H. Niimi ◽  
S. Gandhi ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Rapid Thermal Processing ◽  
Electrical Characterization ◽  
Chemical Vapor ◽  
Silicon Oxynitride ◽  
Dielectric Films ◽  
Mos Capacitor ◽  
Nitride Oxide

ABSTRACTWe have used a combination of plasma and rapid thermal processing for the formation of thin gate-dielectric films. The bulk dielectric films investigated include silicon oxide, oxynitride and multilayer oxide-nitride-oxide heterostructures formed by plasma-assisted oxidation, remoteplasma-enhanced chemical-vapor deposition (remote-PECVD) followed by post-deposition rapid thermal annealing (RTA). Auger electron spectroscopy (AES) and infrared absorption spectroscopy (IR) have been used to study the chemistry of interface formation and the bulk dielectric chemical bonding, respectively. Electrical characterization of MOS capacitor structures incorporating these dielectrics was performed by conventional capacitance and current voltage techniques, C-V and I-V, respectively.

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