Rapid Thermal Processes for Future Nanometer MOS Devices

1998 ◽  
Vol 525 ◽  
Author(s):  
John R. Hauser
Keyword(s):  
Thermal Processing ◽  
Gate Dielectric ◽  
Rapid Thermal Processing ◽  
Dielectric Materials ◽  
Nanometer Scale ◽  
Thermal Processes ◽  
Contact Material ◽  
Mos Devices ◽  
Front End ◽  
Projected Changes

ABSTRACTScaling of MOS devices is projected to continue down to device dimensions of at least 50 nm. However, there are many potential roadblocks to achieving such dimensions and many standard materials and front-end processes which must be significantly changed to achieve these goals. The most important areas for change include (a) gate dielectric materials, (b) gate contact material, (c) source/drain contacting structure and (d) fundamental bulk CMOS structure. These projected changes are reviewed along with possible applications of rapid thermal processing to achieving future nanometer scale MOS devices.

SIMS STUDY OF SILICON OXYNITRIDE RAPID THERMALLY GROWN IN NITRIC OXIDE

2001 ◽  
Vol 08 (05) ◽  
pp. 569-573
Author(s):  
R. LIU ◽  
K. H. KOA ◽  
A. T. S. WEE ◽  
W. H. LAI ◽  
M. F. LI ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Depth Distribution ◽  
Secondary Ion Mass Spectrometry ◽  
Gate Dielectric ◽  
State Of The Art ◽  
Rapid Thermal Processing ◽  
Growth Characteristics ◽  
Silicon Oxynitride ◽  
Mos Devices ◽  
Secondary Ion

As the gate dielectric for ULSI MOS devices scales in the ultrathin regime, it is fabricated increasingly with silicon oxynitride instead of silicon dioxide films. One way to obtain silicon oxynitride films is the rapid thermal oxidation of silicon in NO (RTNO). Earlier RTNO growth studies were not sufficiently comprehensive as well as limited by temperature uncertainty and nonuniformity across the wafer. Using a state-of-the-art rapid thermal processing (RTP) system, RTNO growth characteristics at oxidation pressures of 100 and 760 Torr, oxidation temperatures from 900 to 1200°C and oxidation times from 0 to 480 s were obtained and investigated. Anomalies in the growth characteristics were observed. It was also demonstrated that secondary ion mass spectrometry (SIMS) using the MCs + method could be used to accurately determine the depth distribution of N in ultrathin silicon oxynitride films.

Silicon Oxynitride and Oxide-Nitride-Oxide Gate Dielectrics by Combined Plasma-Rapid Thermal Processing

1994 ◽  
Vol 342 ◽  
Author(s):  
Y. Ma ◽  
S.V. Hattangady ◽  
T. Yasuda ◽  
H. Niimi ◽  
S. Gandhi ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Rapid Thermal Processing ◽  
Electrical Characterization ◽  
Chemical Vapor ◽  
Silicon Oxynitride ◽  
Dielectric Films ◽  
Mos Capacitor ◽  
Nitride Oxide

ABSTRACTWe have used a combination of plasma and rapid thermal processing for the formation of thin gate-dielectric films. The bulk dielectric films investigated include silicon oxide, oxynitride and multilayer oxide-nitride-oxide heterostructures formed by plasma-assisted oxidation, remoteplasma-enhanced chemical-vapor deposition (remote-PECVD) followed by post-deposition rapid thermal annealing (RTA). Auger electron spectroscopy (AES) and infrared absorption spectroscopy (IR) have been used to study the chemistry of interface formation and the bulk dielectric chemical bonding, respectively. Electrical characterization of MOS capacitor structures incorporating these dielectrics was performed by conventional capacitance and current voltage techniques, C-V and I-V, respectively.

Advanced Dram Cell Dielectric Films using Rapid Thermal Processing

1994 ◽  
Vol 342 ◽  
Author(s):  
Randhir P.S. Thakur ◽  
Viju K. Mathews ◽  
Pierre C. Fazan
Keyword(s):  
Silicon Nitride ◽  
Thermal Processing ◽  
Structural Characteristics ◽  
Rapid Thermal Processing ◽  
Random Access ◽  
Dielectric Materials ◽  
Nonlinear Dependence ◽  
Dielectric Films ◽  
Storage Node ◽  
Carrier Tunneling

ABSTRACTThe reliable operation of a dynamic random access memory (DRAM) device requires a minimum level of charge to be stored in the capacitor. The nonlinear dependence between the scaling of the minimum charge and the cell area for higher DRAM densities is the driving force in the development of exotic capacitor structures and advanced cell dielectric materials. The conventional option of reducing the thickness of the silicon nitride dielectric films for high density DRAM applications will eventually be constrained by the increase in the leakage current due to direct carrier tunneling or by the decrease in the oxidation resistance of the films.In this paper we discuss the use of rapid thermal processing to modify the interface between the polysilicon storage node of the capacitor and the silicon nitride to improve the electrical and structural characteristics without any loss in capacitance. The influence of electrode roughness on the electrical behavior will also be discussed for the various dielectric stack combinations.

Methods to Improve Properties of Gate Dielectrics in Metal-Oxide-Semiconductor

2012 ◽  
Vol 463-464 ◽  
pp. 1341-1345 ◽  
Author(s):  
Chong Liu ◽  
Xiao Li Fan
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Dielectric Materials ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Physical Limitation ◽  
Low Leakage ◽  
Mos Devices ◽  
Low Leakage Current ◽  
High K

This essay aims to introduce development of gate dielectrics. In present-day society, Si-based MOS has met its physical limitation. Scientists are trying to find a better material to reduce the thickness and dimension of MOS devices. While substrate materials are required to have a higher mobility, gate dielectrics are expected to have high k, low Dit and low leakage current. I conclude dielectrics in both Si-based and Ge-based MOS devices and several measures to improve the properties of these gate dielectric materials. I also introduce studies on process in our group and some achievements we have got. Significantly, this essay points out the special interest in rare-earth oxides functioning as gate dielectrics in recent years and summarizes the advantages and problems should be resolved in future.

Integrated Rapid Thermal CVD Processing Solutions for 0.18–0.25μm Technologies

1997 ◽  
Vol 470 ◽  
Author(s):  
H. Gilboa ◽  
Y. E. Gilboa ◽  
Z. Atzmon ◽  
S. Levy ◽  
H. Spilberg ◽  
...  
Keyword(s):  
High Temperature ◽  
Flash Memory ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Chemical Vapor ◽  
Wafer Cleaning ◽  
Front End ◽  
Wafer Processing ◽  
Cluster Tool ◽  
Temperature Applications

ABSTRACTThe evolution of integrated single-wafer processing for high-temperature applications in the front end of the line (FEOL) occurred with the advancements in single-wafer rapid thermal processing and its acceptance as a manufacturing technology. The Integra RTCVD cluster tool for high-temperature applications features wafer cleaning, rapid thermal processing and single wafer chemical vapor deposition steps. The paper presents integrated vapor phase clean and RTCVD applications for FLASH memory gate stack and DRAM cell.

A physical model for boron penetration through an oxynitride gate dielectric prepared by rapid thermal processing in N2O

1991 ◽  
Vol 59 (13) ◽  
pp. 1581-1582 ◽  
Author(s):  
Hyunsang Hwang ◽  
Wenchi Ting ◽  
Dim‐Lee Kwong ◽  
Jack Lee
Keyword(s):  
Physical Model ◽  
Thermal Processing ◽  
Gate Dielectric ◽  
Rapid Thermal Processing ◽  
Boron Penetration

Fabrication of 4H-SiC DIMOSFETs by High-Temperature (>1400°C) Rapid Thermal Oxidation and Nitridation Using Cold-Wall Oxidation Furnace

2006 ◽  
Vol 527-529 ◽  
pp. 1309-1312
Author(s):  
Ryouji Kosugi ◽  
Kenji Suzuki ◽  
Kazuto Takao ◽  
Yusuke Hayashi ◽  
Tsutomu Yatsuo ◽  
...  
Keyword(s):  
High Temperature ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Thermal Processes ◽  
Cold Wall ◽  
Channel Mobility ◽  
Blocking Voltage ◽  
Interfacial Defects ◽  
Maximum Process ◽  
Short Time

A passivation annealing in nitric oxide (NO) ambient significantly reduces the interfacial defects of the SiO2/4H-SiC interface and improves the inversion MOS channel mobility. Effects of the nitridation in NO ambient become more pronounced at high temperatures in general. However, the maximum process temperature in a standard hot-wall oxidation furnace is restricted around 1200oC due to the softening point of quartz. Meanwhile, by use of a cold-wall oxidation furnace, high temperature and short time thermal processes become possible. In this study, we have developed an extremely high temperature (>1400oC) rapid thermal processing for the gate oxidation in the 4H-SiC DIMOSFET fabrication process. The peak MOS channel mobility of lateral MOSFETs on the DIMOSFET chip shows as high as 19cm2/Vs. The specific on-resistance of the device was 12.5mcm2 and the blocking voltage was 950V with gate shorted to the source.

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