scholarly journals Design of Low Power Multiplexer and De-Multiplexer using Different Adiabatic Logics

2020 ◽  
Vol 9 (1) ◽  
pp. 465-473
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Digital Circuit ◽  
Logic Circuits ◽  
Digital Circuit Design ◽  
Adiabatic Logic ◽  
Low Power Dissipation ◽  
In Series ◽  
Main Factor

In this paper we proposed, design and evaluation of 16:1 Multiplexer and 1:16 Demultiplexer using different adiabatic logics. Power consumption is the main factor in VLSI digital circuit design. Here we have introduced a CMOS-logic based 16:1 Multiplexer and 1:16 De-multiplexer with a low power adiabatic logic. In which we concentrate on the characteristics of the CMOS and adiabatic logics such as 2N2P, 2N-2N2P and Dual sleep. Wherein both 2N2P and 2N2N2P use a cross-coupled transistor structure for adiabatic operation. Adiabatic logic circuits use reverse logic and the power dissipation will be less compared to the CMOS circuits as the inputs are given to the n-type functional tree in 2N2P and 2N2N2P. For dual sleep logic an additional circuit is connected in series with general CMOS circuit known as sleep circuit. we have concentrated on energy recovery and power dissipation, as all these technique results in the low power dissipation. Dualsleep is considered as the best of the all the other adiabatic and traditional logics

scholarly journals A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

2019 ◽  
Vol 8 (3) ◽  
pp. 162
Author(s):  
Pritty Pritty ◽  
Manoj Kumar ◽  
Mariyam Zunairah
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Full Adder ◽  
Digital Circuit ◽  
Xor Gate ◽  
Digital Circuit Design ◽  
Result Show ◽  
Body Bias

Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

2014 ◽  
Vol 23 (05) ◽  
pp. 1450066
Author(s):  
JITENDRA KANUNGO ◽  
S. DASGUPTA
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Energy Recovery ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Sense Amplifier ◽  
Simulation Based ◽  
Digital Circuit Design

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

scholarly journals Approximate arithmetic circuits

2020 ◽  
Vol 9 (3) ◽  
pp. 183
Author(s):  
Navabharath Reddy G ◽  
Sruti Setlam ◽  
V. Prakasam ◽  
D. Kiran Kumar
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Integrated Circuit Design ◽  
Compressor Design ◽  
Low Power Dissipation ◽  
Human Sense ◽  
Error Distance

Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia ap- plications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation isless, the output of the DSP blocks allows being numerically approx- imate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. Approximate 4-2 compressor was proposed in this project to reduce number of partial produt. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW)which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.

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