Effective file data-block placement for different types of page cache on hybrid main memory architectures

Like many open-source technologies such as UNIX or TCP/IP, Hadoop was not created with Security in mind. Hadoop however evolved from the other tools over time and got widely adopted across large enterprises. Some of Hadoop’s architectural features present Hadoop its unique security issues. Given this security vulnerability and potential invasion of confidentiality due to malicious attackers or internal customers, organizations face challenges in implementing a strong security framework for Hadoop. Furthermore, given the method in which data is placed in Hadoop Cluster adds to the only growing list of these potential security vulnerabilities. Data privacy is compromised when these critical and data-sensitive blocks are accessed either by unauthorized users or for that matter even misuse by authorized users. In this paper, we intend to address the strategy of data block placement across the allotted DataNodes. Prescriptive analytics algorithms are used to determine the Sensitivity Index of the Data and thereby decide on data placement allocation to provide impenetrable access to an unauthorized user. This data block placement strategy aims to adaptively distribute the data across the cluster using innovative ML techniques to make the data infrastructure extra secured.

Download Full-text

Hadoop distributed file system mechanism for processing of large datasets across computers cluster using programming techniques

International Research Journal of Management IT and Social Sciences ◽

10.21744/irjmis.v6n6.739 ◽

2019 ◽

Vol 6 (6) ◽

pp. 1-16

Author(s):

Nicholas Jain Edwards ◽

David Tonny Brain ◽

Stephen Carinna Joly ◽

Mariana Karry Masucato

Keyword(s):

Main Memory ◽

Data Block ◽

Source Node ◽

Hadoop Distributed File System ◽

Programming Techniques ◽

Source Block ◽

Operations Performance ◽

Time Required ◽

Fully Connected ◽

Cache Design

In this paper, we have proved that the HDFS I/O operations performance is getting increased by integrating the set associativity in the cache design and changing the pipeline topology using fully connected digraph network topology. In read operation, since there is huge number of locations (words) at cache compared to direct mapping the chances of miss ratio is very low, hence reducing the swapping of the data between main memory and cache memory. This is increasing the memory I/O operations performance. In Write operation instead of using the sequential pipeline we need to construct the fully connected graph using the data blocks listed from the NameNode metadata. In sequential pipeline, the data is getting copied to source node in the pipeline. Source node will copy the data to next data block in the pipeline. The same copy process will continue until the last data block in the pipeline. The acknowledgment process has to follow the same process from last block to source block. The time required to transfer the data to all the data blocks in the pipeline and the acknowledgment process is almost 2n times to data copy time from one data block to another data block (if the replication factor is n).

Download Full-text

A Survey of Hybrid Main Memory Architectures

Sakarya University Journal of Science ◽

10.16984/saufenbilder.334645 ◽

2019 ◽

pp. 1-1

Author(s):

Zerrin YILDIZ ÇAVDAR ◽

İsa AVCI ◽

Murat KOCA ◽

Ahmet SERTBAŞ

Keyword(s):

Main Memory ◽

Memory Architectures

Download Full-text

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Electronics ◽

10.3390/electronics11020240 ◽

2022 ◽

Vol 11 (2) ◽

pp. 240

Author(s):

Beomjun Kim ◽

Yongtae Kim ◽

Prashant Nair ◽

Seokin Hong

Keyword(s):

Random Access ◽

Spin Transfer Torque ◽

Main Memory ◽

Spin Transfer ◽

Access Memory ◽

Low Leakage ◽

Block Placement ◽

On Chip ◽

Hybrid Caches ◽

Cache Block

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

Download Full-text

Histaminergic Mechanisms for Modulation of Memory Systems

Neural Plasticity ◽

10.1155/2011/328602 ◽

2011 ◽

Vol 2011 ◽

pp. 1-16 ◽

Cited By ~ 34

Author(s):

Cristiano André Köhler ◽

Weber Cláudio da Silva ◽

Fernando Benetti ◽

Juliana Sartori Bonini

Keyword(s):

Memory Systems ◽

Memory Formation ◽

Main Memory ◽

Histaminergic System ◽

Receptor Agonists ◽

Different Types ◽

Behavioral Tasks ◽

Feeding Rhythms ◽

The Brain

Encoding for several memory types requires neural changes and the activity of distinct regions across the brain. These areas receive broad projections originating in nuclei located in the brainstem which are capable of modulating the activity of a particular area. The histaminergic system is one of the major modulatory systems, and it regulates basic homeostatic and higher functions including arousal, circadian, and feeding rhythms, and cognition. There is now evidence that histamine can modulate learning in different types of behavioral tasks, but the exact course of modulation and its mechanisms are controversial. In the present paper we review the involvement of the histaminergic system and the effects histaminergic receptor agonists/antagonists have on the performance of tasks associated with the main memory types as well as evidence provided by studies with knockout models. Thus, we aim to summarize the possible effects histamine has on modulation of circuits involved in memory formation.

Download Full-text