Ultra low-k die crack study for lead free solder bump flip-chip packaging

2010 ◽  
Vol 22 (8) ◽  
pp. 988-994 ◽  
Author(s):  
K. M. Chen
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Lead Free ◽  
Lead Free Solder ◽  
Flip Chip Packaging ◽  
Free Solder ◽  
Low K

Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Thermally Activated ◽  
Fine Pitch ◽  
Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

Low-Stress Interconnection for Flip Chip BGA Employing Lead-Free Solder Bump

2007 ◽  
Author(s):  
Masayuki Uchida ◽  
Hisashi Ito ◽  
Ken Yabui ◽  
Hideo Nishiuchi ◽  
Takashi Togasaki ◽  
...  
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

Precise Quantitative Evaluation of Nano-Ordered Intermetallic Compounds in Sn-3.0Ag-0.5Cu Lead-Free Solder Bump by Using TEM

2008 ◽  
Vol 47-50 ◽  
pp. 907-911
Author(s):  
Chang Woo Lee ◽  
Y.S. Shin ◽  
J.H. Kim
Keyword(s):  
Intermetallic Compounds ◽  
Flip Chip ◽  
Solder Bump ◽  
Lead Free Solder ◽  
Growth Behaviour ◽  
Sic Particles ◽  
Imcs Growth ◽  
Ordered Intermetallic ◽  
Free Solder ◽  
The One

The growth behaviour of the intermetallic compounds (IMCs) in Pb-free solder bump is investigated. The Pb-free micro-bump, Sn-50%Bi, was fabricated by binary electroplating for flip-chip bond. The diameter of the bump is about 506m and the height is about 60 6m. In order to increase the reliability of the bonding, it is necessary to protect the growth of the IMCs in interface between Cu pad and the solder bump. For control of IMCs growth, SiC particles were distributed in the micro-solder bump during electroplating. The thickness of the IMCs in the interface was estimated by FE-SEM, EDS, XRF and TEM. From the results, The IMCs were found as Cu6Sn5 and Cu3Sn. The thickness of the IMCs decreases with increase the amount of SiC particles until 4 g/cm2. The one candidate of the reasons is that the SiC particles could decrease the area which be reacted between the solder and Cu layer. And another candidate is that the particle can make to difficult inter-diffusion within the interface.

scholarly journals Growth Kinetics of Reaction Layers in Flip Chip Joints with Cu-cored Lead-free Solder Balls

2004 ◽  
Vol 45 (3) ◽  
pp. 754-758 ◽  
Author(s):  
Ikuo Shohji ◽  
Yuji Shiratori ◽  
Hiroshi Yoshida ◽  
Masahiko Mizukami ◽  
Akira Ichida
Keyword(s):  
Growth Kinetics ◽  
Flip Chip ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Balls ◽  
Free Solder ◽  
Kinetics Of Reaction ◽  
Kinetics Of

Practical Application and Analysis of Lead-Free Solder on Chip-On-Flip-Chip SiP for Hearing Aids

2017 ◽  
Vol 2017 (1) ◽  
pp. 000201-000207 ◽  
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Hearing Aids ◽  
Flip Chip ◽  
Failure Modes ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Practical Application ◽  
Surface Mount ◽  
Free Solder ◽  
On Chip

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Considerable amount of defects associated with solder overflow are found on chip-on-flip-chip (COFC) SiP in hearing aids. Through the use of design of experiments (DOE), lead-free solder defect causes on hearing aids application can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components for hearing aid applications. The practical application and analysis of lead-free solder for hearing aids will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types through the DOE process.

Study on electromigration in flip chip lead-free solder connections with 40 μm or 30 μm diameter on thin film ceramic substrates

2015 ◽  
Vol 2015 (1) ◽  
pp. 000799-000805
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Bernd Kandler ◽  
Bernd Burger
Keyword(s):  
Thin Film ◽  
High Stability ◽  
Flip Chip ◽  
Lead Free ◽  
Published Data ◽  
Organic Substrates ◽  
Lead Free Solder ◽  
Ceramic Substrates ◽  
Solder Bumps ◽  
Free Solder

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Comparative Modeling and Analysis of Lead-Free Solder Extrusion for the Design of Reliability

2016 ◽  
Vol 2016 (1) ◽  
pp. 000111-000116
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Design Of Experiments ◽  
Flip Chip ◽  
Failure Modes ◽  
Form Factors ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Modeling And Analysis ◽  
Surface Mount ◽  
Free Solder

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Through the use of design of experiments (DOE), lead-free solder defect causes can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components. The systematic investigation will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types utilizing the design of experiments methods.

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