Controlling of Floating-Body and Thermal Conductivity in Short Channel SOI MOSFET at 30 nm Channel Node

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

Download Full-text

Improving Short Channel Effects by Reformed U-Channel UTBB FD SOI MOSFET: A Feasible Scaled Device

Silicon ◽

10.1007/s12633-020-00861-z ◽

2021 ◽

Author(s):

Moslem Ghassemi ◽

Ali A. Orouji

Keyword(s):

Short Channel Effects ◽

Short Channel ◽

Soi Mosfet ◽

Channel Effects

Download Full-text

STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

Jurnal Teknologi ◽

10.11113/jt.v77.6616 ◽

2015 ◽

Vol 77 (21) ◽

Author(s):

M.N.I.A Aziz ◽

F. Salehuddin ◽

A.S.M. Zain ◽

K.E. Kaharudin

Keyword(s):

Thin Film ◽

Electrical Characteristic ◽

Silicon On Insulator ◽

Electrical Characteristics ◽

Short Channel ◽

Doping Density ◽

Soi Mosfet ◽

Buried Oxide ◽

Soi Technology ◽

Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

Download Full-text

Inspection for critical issue of floating body effects in SOI-MOSFET using nuclear particles

Digest of Papers. Microprocesses and Nanotechnology 2001. 2001 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.01EX468) ◽

10.1109/imnc.2001.984077 ◽

2002 ◽

Author(s):

S. Abo ◽

M. Mizutani ◽

K. Nakayama ◽

T. Takaoka ◽

T. Iwamatsu ◽

...

Keyword(s):

Critical Issue ◽

Floating Body ◽

Soi Mosfet ◽

Floating Body Effects

Download Full-text

Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Journal of Nanotechnology ◽

10.1155/2019/4935073 ◽

2019 ◽

Vol 2019 ◽

pp. 1-12 ◽

Cited By ~ 1

Author(s):

Anjali Priya ◽

Nilesh Anand Srivastava ◽

Ram Awadh Mishra

Keyword(s):

Threshold Voltage ◽

Propagation Delay ◽

Silicon On Insulator ◽

Device Performance ◽

Gate Length ◽

Metal Gate ◽

Short Channel ◽

Fully Depleted ◽

Soi Mosfet ◽

Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Download Full-text