Effect of Positive/Negative Interface Trap Charges on the Performance of Multi Fin FinFET (M-FinFET)

Silicon ◽

10.1007/s12633-022-01669-9 ◽

2022 ◽

Author(s):

Rinku Rani Das ◽

Santanu Maity ◽

Atanu Chowdhury ◽

Apurba Chakraborty ◽

Suman Kumar Mitra

Keyword(s):

Interface Trap ◽

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Analytical drain current model to study the impact of interface trap charges on device performance of Double Gate Ge Ferroelectric FET (DGGeFeFET)

2018 Conference on Emerging Devices and Smart Systems (ICEDSS) ◽

10.1109/icedss.2018.8544314 ◽

2018 ◽

Author(s):

Monika Bansal ◽

Harsupreet Kaur

Keyword(s):

Current Model ◽

Drain Current ◽

Interface Trap ◽

Device Performance ◽

Double Gate ◽

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Evaluation of Analog Circuit Performance for Ferroelectric SOI MOSFETs considering Interface Trap Charges and Gate Length Variations

2019 Silicon Nanoelectronics Workshop (SNW) ◽

10.23919/snw.2019.8782942 ◽

2019 ◽

Author(s):

Yi-Chun Lu ◽

Vita Pi-Ho Hu

Keyword(s):

Analog Circuit ◽

Interface Trap ◽

Gate Length ◽

Circuit Performance ◽

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Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges

IEEE Transactions on Electron Devices ◽

10.1109/ted.2019.2935342 ◽

2019 ◽

Vol 66 (10) ◽

pp. 4453-4460 ◽

Author(s):

Naveen Kumar ◽

Ashish Raman

Keyword(s):

Performance Assessment ◽

Interface Trap ◽

Charge Plasma ◽

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Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability

Micro & Nano Letters ◽

10.1049/mnl.2017.0869 ◽

2018 ◽

Vol 13 (8) ◽

pp. 1192-1196

Author(s):

Sarthak Gupta ◽

Dheeraj Sharma ◽

Deepak Soni ◽

Shivendra Yadav ◽

Mohd. Aslam ◽

...

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Gate Dielectric ◽

Interface Trap ◽

Material Control ◽

Device Reliability ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Dual Material ◽

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Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric

IEEE Transactions on Device and Materials Reliability ◽

10.1109/tdmr.2017.2653620 ◽

2017 ◽

Vol 17 (1) ◽

pp. 245-252 ◽

Author(s):

Pulimamidi Venkatesh ◽

Kaushal Nigam ◽

Sunil Pandey ◽

Dheeraj Sharma ◽

Pravin N. Kondekar

Keyword(s):

Gate Dielectric ◽

Interface Trap ◽

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Investigation of interface trap charges and temperature variation in heterostacked-TFET

Indian Journal of Physics ◽

10.1007/s12648-020-01834-z ◽

2020 ◽

Author(s):

K. Vanlalawmpuia ◽

Brinda Bhowmick

Keyword(s):

Temperature Variation ◽

Interface Trap ◽

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Effect of interface trap charges on the performance of asymmetric dielectric modulated dual short gate tunnel FET

AEU - International Journal of Electronics and Communications ◽

10.1016/j.aeue.2019.02.007 ◽

2019 ◽

Vol 102 ◽

pp. 1-8 ◽

Author(s):

Adhithan Pon ◽

Kuralla Sivanaga Venkata Poorna Tulasi ◽

R. Ramesh

Keyword(s):

Interface Trap ◽

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Impact of Interface Trap Charges on the Electrical Characteristics of Back-Gated 2D Negative Capacitance (NC) FET

IEEE Transactions on Nanotechnology ◽

10.1109/tnano.2019.2950668 ◽

2019 ◽

Vol 18 ◽

pp. 1204-1207

Author(s):

Chunsheng Jiang ◽

Le Zhong ◽

Lei Xie

Keyword(s):

Interface Trap ◽

Negative Capacitance ◽

Electrical Characteristics ◽

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Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET

IEEE Transactions on Electron Devices ◽

10.1109/ted.2017.2754297 ◽

2017 ◽

Vol 64 (11) ◽

pp. 4731-4737 ◽

Author(s):

Sarthak Gupta ◽

Kaushal Nigam ◽

Sunil Pandey ◽

Dheeraj Sharma ◽

Pravin N. Kondekar

Keyword(s):

Gate Dielectric ◽

Interface Trap ◽

Performance Variation ◽

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Temperature associated reliability analysis of a Si/Ge Heterojunction Dopingless Tunnel FET considering Interface Trap Charges

2021 Devices for Integrated Circuit (DevIC) ◽

10.1109/devic50843.2021.9455866 ◽

2021 ◽

Author(s):

Suruchi Sharma ◽

Rikmantra Basu ◽

Baljit Kaur

Keyword(s):

Reliability Analysis ◽

Interface Trap ◽

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