A hybrid-mode bulk-driven folded cascode OTA with enhanced unity-gain bandwidth and slew rate

A low power current recycling constant-gm rail-to-rail (RtR) OTA is presented. The proposed amplifier has the benefit of delivering the same performance while consuming half the power compared to the conventional RtR amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in CSMC standard 0.18 um CMOS process. Simulation results show that the proposed amplifier achieves 10.2 MHz unity-gain bandwidth, 59.4 dB DC gain, 4.8 V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional RtR amplifier with the same design specifications.

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A Start-up Assisted Fully Differential Folded Cascode Opamp

Journal of Circuits System and Computers ◽

10.1142/s0218126619501640 ◽

2019 ◽

Vol 28 (10) ◽

pp. 1950164 ◽

Cited By ~ 4

Author(s):

R. Nagulapalli ◽

K. Hayatleh ◽

S. Barker ◽

B. Yassine ◽

S. Zourob ◽

...

Keyword(s):

Monte Carlo ◽

Positive Feedback ◽

Cmos Technology ◽

Gain Bandwidth ◽

Fully Differential ◽

Start Up ◽

Unity Gain ◽

Folded Cascode ◽

Current Selection ◽

Latch Up

This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87[Formula: see text]dB, 250[Formula: see text]MHz unity gain bandwidth amplifier has been developed in 65[Formula: see text]nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126[Formula: see text][Formula: see text]A from a 1.2[Formula: see text]V supply and occupies the 2184[Formula: see text][Formula: see text]m2 area.

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An Output-Capacitorless Low-Dropout Regulator with High Slew Rate and Unity-Gain Bandwidth

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9181142 ◽

2020 ◽

Author(s):

Yong Zhou ◽

Yanqi Zheng ◽

Ka Nang Leung

Keyword(s):

Slew Rate ◽

Gain Bandwidth ◽

Unity Gain ◽

Low Dropout Regulator

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Design of High Gain CMOS Folded Cascode Operational Amplifier

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.389.573 ◽

2013 ◽

Vol 389 ◽

pp. 573-578

Author(s):

Ming Xin Song ◽

Yue Li ◽

Meng Meng Xu

Keyword(s):

Power Supply ◽

Operational Amplifier ◽

High Gain ◽

Cmos Process ◽

Phase Margin ◽

Gain Bandwidth ◽

Input Stage ◽

Dc Gain ◽

Unity Gain ◽

Folded Cascode

A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

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Design of a Gain-Boosted Cascode Amplifier with High Unity-Bandwidth

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.614.237 ◽

2014 ◽

Vol 614 ◽

pp. 237-240

Author(s):

Lin Feng Wang ◽

Qiao Meng ◽

Hao Zhi

Keyword(s):

Direct Current ◽

Cmos Technology ◽

Gain Bandwidth ◽

Fully Differential ◽

Common Mode Voltage ◽

Dc Gain ◽

Unity Gain ◽

Folded Cascode ◽

The Stability ◽

Cascode Amplifier

This paper presents a high unity gain bandwidth fully differential folded-cascode operational amplifier using gain-boosted technique. The amplifier is designed in TSMC 0.18μm 1P6M CMOS technology. The unity-gain bandwidth (GBW) and poles of the gain-boosting amplifiers were carefully designed to improve the stability. The implemented design provides a direct current (DC) gain of around 93 dB with a unity gain frequency of 1.8GHz. It exhibits a DC gain larger than 88dB when the output common-mode voltage between 0.6 V and 1.2V. the overall layout size is 96μm×120μm.

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