Surface characterisation and interface studies of high-k materials by XPS and TOF-SIMS

2005 ◽  
Vol 252 (1) ◽  
pp. 172-176 ◽  
Author(s):  
A. Besmehn ◽  
A. Scholl ◽  
E. Rije ◽  
U. Breuer
Keyword(s):  
Surface Characterisation ◽  
Tof Sims ◽  
High K ◽  
High K Materials

Composition Quantification of Microelectronics Multilayer Thin Films by EDX: Toward Small Scale Analysis

2009 ◽  
Vol 1184 ◽  
Author(s):  
Thierry Conard ◽  
Kai Arstila ◽  
Thomas Hantschel ◽  
Alexis Franquet ◽  
Wilfried Vandervorst ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Small Scale ◽  
Quantitative Composition ◽  
Composition Analysis ◽  
Multilayer Thin Films ◽  
Large Area ◽  
Fast Analysis ◽  
Metal Gates ◽  
High K ◽  
High K Materials

AbstractIn order to continuously improve the performances of microelectronics devices through scaling, SiO2 is being replaced by high-k materials as gate dielectric; metal gates are replacing poly-Si. This leads to increasingly more complex stacks. For future generations, the replacement of Si as a substrate by Ge and/or III/V material is also considered. This also increases the demand on the metrology tools as a thorough characterization, including composition and thickness is thus needed. Many different techniques exist for composition analysis. They usually require however large area for the analysis, complex instrumentation and can be time consuming. EDS (Energy Dispersive Spectroscopy) when coupled to Scanning Electron Microscopy (SEM) has the potential to allow fast analysis on small scale areas.In this work, we evaluate the possibilities of EDS for thin film analysis based on an intercomparison of composition analysis with different techniques. We show that using proper modeling, high quality quantitative composition and thickness of multilayers can be achieved.

Study on deposition kinetics of high-K materials by X-ray fluorescence techniques

2004 ◽  
Vol 59 (8) ◽  
pp. 1183-1187 ◽  
Author(s):  
Caterina Carpanese ◽  
Barbara Crivelli ◽  
Massimo Caniatti
Keyword(s):  
X Ray ◽  
Deposition Kinetics ◽  
Fluorescence Techniques ◽  
High K ◽  
High K Materials ◽  
Kinetics Of

Suppressing the loss and enhancing the breakdown strengths of high-k materials via constructing layered structure

2022 ◽  
pp. 131654
Author(s):  
Shuimiao Xia ◽  
Zhicheng Shi ◽  
Liang Sun ◽  
Shengbiao Sun ◽  
Davoud Dastan ◽  
...  
Keyword(s):  
Layered Structure ◽  
High K ◽  
High K Materials

Design, Simulation and Testing of High Density, High Current Micro-machined Embedded Capacitors

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000515-000534
Author(s):  
Aubrey Beal ◽  
C. Stevens ◽  
T. Baginski ◽  
M. Hamilton ◽  
R. Dean
Keyword(s):  
Integrated Circuits ◽  
Hafnium Oxide ◽  
Implementation Strategies ◽  
Atomic Layer ◽  
High Density ◽  
Embedded Capacitors ◽  
Passive Devices ◽  
Layer Deposition ◽  
High K ◽  
High K Materials

Due to increasing speed, density and number of signal paths in integrated circuits, motivations for high density capacitors capable of quickly sourcing large amounts of current have led to many design and fabrication investigations. This work outlines continued efforts to achieve devices which meet these stringent requirements and are compatible with standard silicon fabrication processes as well as silicon interposer technologies. Previous work has been further developed resulting in devices exhibiting greater capacitance values by employing geometries which maximize surface area. The Atomic Layer Deposition (ALD) of thin layered high K materials, such as Hafnium Oxide, as opposed to previous silicon-dioxide based devices effectively increased the capacitance per unit area of the structures. This paper outlines the design, fabrication, and testing of high density micro-machined embedded capacitors capable of quickly sourcing (i.e. risetimes greater than 100A/nsec) high currents (i.e. greater than 100A). These devices were successfully simulated then tested using a standard ringdown procedure. Generally, the resulting device characterization found during testing stages strongly correlates to the expected simulated device behavior. Subsequent descriptions and design challenges encountered during fabrication, testing and integration of these passive devices are outlined, as well as potential device integration and implementation strategies for use in silicon interposers. The modification and revision of several device generations is documented and presented. Increased device capacitive density, maximized current capabilities and minimized effects of series inductance and resistance are presented. These resulting thin, capacitive structures exhibit compatibility with Si interposer technology.

Design Considerations and Ring-down Characteristics of Micromachined, High Current Density Capacitors

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001380-001406
Author(s):  
Aubrey N. Beal ◽  
John Tatarchuk ◽  
Colin Stevens ◽  
Thomas Baginski ◽  
Michael Hamilton ◽  
...  
Keyword(s):  
Energy Storage ◽  
Surface Area ◽  
High Density ◽  
Energy Storage Devices ◽  
Capacitive Energy Storage ◽  
Passive Components ◽  
Storage Devices ◽  
Passive Devices ◽  
High K ◽  
High K Materials

The need for integrated passive components which meet the stringent power system requirements imposed by increased data rates, signal path density and challenging power distribution network topologies in integrated systems yield diverse motivations for high density, miniaturized capacitors capable of quickly sourcing large quantities of current. These diverse motivations have led to the realization of high density capacitor structures through the means of several technologies. These structures have been evaluated as high-speed, energy storage devices and their respective fabrication technologies have been closely compared for matching integrated circuit speed and density increase, chip current requirements, low resistance, low leakage current, high capacitance and compatibility with relatively high frequencies of operation (~1GHz). These technologies include devices that utilize pn junctions, Schottky barriers, optimized surface area techniques and the utilization of high dielectric constant (high-K) materials, such as hafnium oxide, as a dielectric layer through the means of atomic layer deposition (ALD). The resulting devices were micro-machined, large surface area, thin, high-density capacitor technologies optimized as embedded passive devices for thin silicon interposers. This work outlines the design, fabrication, simulation and testing of each device revision using standard silicon microfabrication processes and silicon interposer technologies. Consequently, capacitive storage devices were micro-machined with geometries which maximize surface area and exhibit the capability of sourcing 100A of current with a response time greater than 100 A/nsec through the use of thin layered, ALD high-K materials. The simulation and testing of these devices show general agreement when subjected to a standard ring-down procedure. This paper provides descriptions and design challenges encountered during fabrication, testing and integration of these passive devices. In addition, potential device integration and implementation strategies for use in silicon interposers are also provided. The modification and revision of several device generations is documented showing increased device capacitance density, maximized current capabilities and minimized effects of series inductance and resistance. The resulting structures are thin, capacitive devices that may be micro-machined using industry standard Si MEMS processes and are compatible with Si interposer 3D technologies. The subsequent design processes allow integrated passive components to be attached beneath chips in order to maximize system area and minimize the chip real estate required for capacitive energy storage devices.

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

2013 ◽  
Vol 100 (6) ◽  
pp. 803-817 ◽  
Author(s):  
D. Nirmal ◽  
P. Vijayakumar ◽  
P. Patrick Chella Samuel ◽  
Binola K. Jebalin ◽  
N. Mohankumar
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
High K ◽  
High K Materials ◽  
Power Application

A Novel Trapping/Detrapping Model for Defect Profiling in High- $k$ Materials Using the Two-Pulse Capacitance–Voltage Technique

2010 ◽  
Vol 57 (10) ◽  
pp. 2726-2735 ◽  
Author(s):  
D. Ruiz Aguado ◽  
B. Govoreanu ◽  
W. Dong Zhang ◽  
M. Jurczak ◽  
K. De Meyer ◽  
...  
Keyword(s):  
High K ◽  
Capacitance Voltage ◽  
High K Materials

Gadolinium -niobates and -tantalates: Amorphous High-k Materials by Aqueous CSD

2012 ◽  
Vol 159 (6) ◽  
pp. G75-G79 ◽  
Author(s):  
D. Dewulf ◽  
A. Hardy ◽  
S. Van Elshocht ◽  
C. De Dobbelaere ◽  
W. C. Wang ◽  
...  
Keyword(s):  
High K ◽  
High K Materials

High mobility Si-Ge channels and novel high-k materials for nanomosfets

2010 ◽  
Author(s):  
W Yu ◽  
B Zhang ◽  
E Durgun-Özben ◽  
R A Minamisawa ◽  
R Luptak ◽  
...  
Keyword(s):  
High Mobility ◽  
High K ◽  
High K Materials
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