Composition Quantification of Microelectronics Multilayer Thin Films by EDX: Toward Small Scale Analysis

2009 ◽  
Vol 1184 ◽  
Author(s):  
Thierry Conard ◽  
Kai Arstila ◽  
Thomas Hantschel ◽  
Alexis Franquet ◽  
Wilfried Vandervorst ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Small Scale ◽  
Quantitative Composition ◽  
Composition Analysis ◽  
Multilayer Thin Films ◽  
Large Area ◽  
Fast Analysis ◽  
Metal Gates ◽  
High K ◽  
High K Materials

AbstractIn order to continuously improve the performances of microelectronics devices through scaling, SiO2 is being replaced by high-k materials as gate dielectric; metal gates are replacing poly-Si. This leads to increasingly more complex stacks. For future generations, the replacement of Si as a substrate by Ge and/or III/V material is also considered. This also increases the demand on the metrology tools as a thorough characterization, including composition and thickness is thus needed. Many different techniques exist for composition analysis. They usually require however large area for the analysis, complex instrumentation and can be time consuming. EDS (Energy Dispersive Spectroscopy) when coupled to Scanning Electron Microscopy (SEM) has the potential to allow fast analysis on small scale areas.In this work, we evaluate the possibilities of EDS for thin film analysis based on an intercomparison of composition analysis with different techniques. We show that using proper modeling, high quality quantitative composition and thickness of multilayers can be achieved.

Challenges in Integrating the High-K Gate Dielectric Film to the Conventional Cmos Process Flow

2001 ◽  
Vol 670 ◽  
Author(s):  
Avinash Agarwal ◽  
Michael Freiler ◽  
Pat Lysaght ◽  
Loyd Perrymore ◽  
Renate Bergmann ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Film ◽  
Cmos Process ◽  
Gate Stack ◽  
Process Flow ◽  
High K ◽  
High K Materials ◽  
Wet Etch ◽  
The Impact ◽  
High K Gate Dielectric

ABSTRACTZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.

High-k Materials for Advanced Gate Stack Dielectrics: a Comparison of ALCVD and MOCVD as Deposition Technologies

2003 ◽  
Vol 765 ◽  
Author(s):  
Matty Caymax ◽  
H. Bender ◽  
B. Brijs ◽  
T. Conard ◽  
S. DeGendt ◽  
...  
Keyword(s):  
Physical Vapor Deposition ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Dielectric Constants ◽  
Gate Stack ◽  
Interfacial Layers ◽  
High K ◽  
High K Materials ◽  
Gate Dielectric Material ◽  
Deposition Techniques

AbstractIn the quest for ever smaller transistor dimensions, the well-known and reliable SiO2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO2. Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.

ISSUES, ACHIEVEMENTS AND CHALLENGES TOWARDS INTEGRATION OF HIGH-k DIELECTRICS

2002 ◽  
Vol 12 (02) ◽  
pp. 295-304 ◽  
Author(s):  
M. CAYMAX ◽  
S. DE GENDT ◽  
W. VANDERVORST ◽  
M. HEYNS ◽  
H. BENDER ◽  
...  
Keyword(s):  
Carrier Mobility ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Interface Layer ◽  
Layer Growth ◽  
Electrical Characteristics ◽  
High K ◽  
Alternative Materials ◽  
High K Materials ◽  
Electrical Reliability

Once the thickness of the gate dielectric layer in CMOS devices gets thinner than 1.2 nm, excessive gate leakage due to direct tunneling makes the use of alternative materials obligatory. Candidate high-k materials are metal oxides such as Al 2 O 3, ZrO 2 and HfO 2 as well as their mixtures. Very promising results have been reported world-wide. Here, however, we show that there are a number of issues related to materials and electrical characteristics as well as to processing which are not always recognized and that necessitate more work to find solutions. Among these are problems with density, interface layer growth and island formation which are clearly related to the deposition process. Also thermal instabilities as well as interactions between the high-k material and poly-Si need attention. Further possible show-stoppers are electrical reliability issues and strongly reduced carrier mobility.

scholarly journals Comprehensive identification of sensitive and stable ISFET sensing layer high-k gate based on ISFET/electrolyte models

2019 ◽  
Vol 9 (2) ◽  
pp. 926 ◽  
Author(s):  
Ahmed M. Dinar ◽  
A. S. Mohd Zain ◽  
F. Salehuddin
Keyword(s):  
Surface Potential ◽  
Gate Dielectric ◽  
High Surface ◽  
Binding Model ◽  
High K ◽  
High K Materials ◽  
Sensing Membrane ◽  
Real Experimental Data ◽  
Poor Stability ◽  
Site Binding

The ISFET sensing membrane is in direct contact with the electrolyte solution, determining the starting sensitivity of these devices. A SiO2 gate dielectric shows a low response sensitivity and poor stability. This paper proposes a comprehensive identification of different high-k materials which can be used for this purpose, rather than SiO2. The Gouy-Chapman and Gouy-Chapman-Stern models were combined with the Site-binding model, based on surface potential sensitivity, to achieve the work objectives. Five materials, namely Al2O3, Ta2O5, Hfo2, Zro2 and SN2O3, which are commonly considered for micro-electronic applications, were compared. This study has identified that Ta2O5 have a high surface potential response at around 59mV/pH, and also exhibits high stability in different electrolyte concentrations. The models used have been validated with real experimental data, which achieved excellent agreement. The insights gained from this study may be of assistance to determine the suitability of different materials before progressing to expensive real ISFET fabrication.

Novel Dielectric Materials for Future Transistor Generations

2006 ◽  
Vol 16 (01) ◽  
pp. 221-239 ◽  
Author(s):  
GENNADI BERSUKER ◽  
BYOUNG HUN LEE ◽  
HOWARD R. HUFF
Keyword(s):  
Gate Dielectric ◽  
Dielectric Materials ◽  
Structural Defects ◽  
Electrical Characteristics ◽  
Si Substrate ◽  
Voltage Instability ◽  
Fixed Charges ◽  
High K ◽  
High K Materials

Relations between the electronic properties of high-k materials and electrical characteristics of high-k transistor are discussed. It is pointed out that the intrinsic limitations of these materials from the standpoint of gate dielectric applications are related to the presence of d-electrons, which facilitate high values of the dielectric constant. It is shown that the presence of structural defects responsible for electron trapping and fixed charges, and the dielectrics' tendency for crystallization and phase separation induce threshold voltage instability and mobility degradation in high-k transistors. The quality of the SiO 2-like layer at the high-k/ Si substrate interface, as well as dielectric interaction with the gate electrode, may significantly affect device characteristics.

scholarly journals High-K materials and metal gates for CMOS applications

2015 ◽  
Vol 88 ◽  
pp. 1-41 ◽  
Author(s):  
John Robertson ◽  
Robert M. Wallace
Keyword(s):  
Metal Gates ◽  
High K ◽  
High K Materials

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

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