Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems

2021 ◽  
Vol 108 ◽  
pp. 104962
Author(s):  
Zahra Zareei ◽  
Mehdi Bagherizadeh ◽  
MohammadHossein Shafiabadi ◽  
Yavar Safaei Mehrabani
Keyword(s):  
2017 ◽  
Vol 26 (05) ◽  
pp. 1750082 ◽  
Author(s):  
Yavar Safaei Mehrabani ◽  
Reza Faghih Mirzaee ◽  
Zahra Zareei ◽  
Seyedeh Mohtaram Daryabari

This paper presents a novel inexact full adder based on carbon nanotube field-effect transistors (CNTFET) for approximate computations, which has soared in popularity especially for image processing applications. The proposed design generates the output carry without error. Therefore, the propagation of incorrect value to higher bit positions is avoided. It has the least relative error distance (Relative ED) compared to other approximate full adders reported in the literature. Practical simulations by using MATLAB demonstrate higher peak signal to noise ratio (PSNR) and image quality for motion detector image processing application. HSPICE simulations also confirm the efficiency of the proposed design. Moreover, area occupation is investigated by using electric tool. Power consumption, delay, area and ED are important evaluating factors in this subject. Comparisons are made by a comprehensive parameter (PDAEDP), based on which the new design has 23.8%, 41.5%, 70.5%, 78% and 83.6% higher performance than TGA1, TGA2, AXA1, AXA2 and AXA3, respectively.


2017 ◽  
Vol 5 (4) ◽  
pp. 15
Author(s):  
ISWARIYA S. ◽  
RAJA M. VILASINI ◽  
◽  
Keyword(s):  

2014 ◽  
Vol 31 (5) ◽  
pp. 479
Author(s):  
Yinshui Xia ◽  
Shiheng Wang ◽  
Libo Qian
Keyword(s):  

2004 ◽  
Author(s):  
S. J. Levinson ◽  
Stephan Bless

Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.


Author(s):  
Mehedi Hasan ◽  
Sharnali Islam ◽  
Mainul Hossain ◽  
Hasan U. Zaman
Keyword(s):  

Author(s):  
Rafael N. M. Oliveira ◽  
Fabio G. R. G. da Silva ◽  
Ricardo Reis ◽  
Cristina Meinhardt
Keyword(s):  

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