Testing single via related defectsin digital VLSI designs

2021 ◽  
Vol 120 ◽  
pp. 114100
Author(s):  
Nunzio Mirabella ◽  
Maurizio Ricci ◽  
Ignazio Calà ◽  
Roberto Lanza ◽  
Michelangelo Grosso
Keyword(s):  
2020 ◽  
Vol 8 ◽  
pp. 14-21
Author(s):  
Surya Man Koju ◽  
Nikil Thapa

This paper presents economic and reconfigurable RF based wireless communication at 2.4 GHz between two vehicles. It implements digital VLSI using two Spartan 3E FPGAs, where one vehicle receives the information of another vehicle and shares its own information to another vehicle. The information includes vehicle’s speed, location, heading and its operation, such as braking status and turning status. It implements autonomous vehicle technology. In this work, FPGA is used as central signal processing unit which is interfaced with two microcontrollers (ATmega328P). Microcontroller-1 is interfaced with compass module, GPS module, DF Player mini and nRF24L01 module. This microcontroller determines the relative position and the relative heading as seen from one vehicle to another. Microcontroller-2 is used to measure the speed of vehicle digitally. The resulting data from these microcontrollers are transmitted separately and serially through UART interface to FPGA. At FPGA, different signal processing such as speed comparison, turn comparison, distance range measurement and vehicle operation processing, are carried out to generate the voice announcement command, warning signals, event signals, and such outputs are utilized to warn drivers about potential accidents and prevent crashes before event happens.


Author(s):  
Brian White ◽  
Mohamed I. Elmasry
Keyword(s):  

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.


2015 ◽  
Vol 23 (3) ◽  
pp. 842-854 ◽  
Author(s):  
Macarena Cristina Martinez-Rodriguez ◽  
Piedad Brox ◽  
Iluminada Baturone

Sign in / Sign up

Export Citation Format

Share Document