Assessment of SiGe/Si heterojunction tunnel field-effect transistor for digital VLSI circuit applications

2019 ◽  
pp. 47-62
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Vlsi Circuit ◽  
Digital Vlsi ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

scholarly journals Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

2021 ◽  
Author(s):  
Md Azmot Ullah Khan ◽  
Naheem Olakunle Adesina ◽  
Jian Xu
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Ring Oscillator ◽  
Limiting Factor ◽  
Vlsi Circuit ◽  
Half Adder ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Output Characteristics ◽  
Power Delay Product

Abstract This paper presents the design of an inverter, half adder, and ring oscillator using compact models of MoS2 channel-based tunnel field effect transistor (TFET). The TFET models (both n and p-type) are written in high-level hardware language Verilog-Analog (Verilog-A) following the analytical model of [1] and the output characteristics of the components are simulated in Cadence/Spectre software. The performance of the designed inverter (a basic building block of VLSI circuit) is analyzed by extracting its different parameters, such as transfer characteristics, power dissipation and consumption, delay, power delay product. The simulated outputs (sum & carry) obtained from the half adder circuit exactly match the truth table of the circuit. Moreover, our observation reveals that the ring oscillator can operate at a higher frequency with lower power consumption in comparison to the existing CMOS and GFET technologies. We have also reported an improvement to the limiting factor of ring oscillator performance i.e. phase noise at two different offset frequencies. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low-power VLSI circuit.

scholarly journals Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

2021 ◽  
Author(s):  
Md Azmot Ullah Khan ◽  
Naheem Olakunle Adesina ◽  
Ashok Srivast ◽  
Jian Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Ring Oscillator ◽  
Vlsi Circuit ◽  
Half Adder ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract This paper presents a newly designed physics-based analytical current transport model of both n- and p-type MoS2 tunnel field-effect transistor (TFET) using a high-level hardware language Verilog-Analog (Verilog-A) within Cadence/Spectre. The performance of our model is analysed by extracting different parameters, including transfer characteristics, power dissipation, and consumption, delay, power delay product (PDP) from the designed inverter. Moreover, we design a ring oscillator, and a half adder circuit to assess the compatibility of our model in both the analog and digital circuits. Our observation reveals that the voltage-controlled oscillator (VCO) can operate at a frequency of 31.6 GHz with a power consumption of 0.083 mW, and generates a phase noise of -122.5 dBc/Hz at 1MHz offset frequency. The simulated outputs (sum & carry) obtained from the half adder circuit exactly match the truth table of the circuit. Last, we present a comparison, using the performance parameters, of the ring oscillator with existing CMOS and GFET technologies. The results show that our designed VCO oscillates at a higher frequency with low power consumption and improved phase noise performance. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low power VLSI circuit.

Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer

2010 ◽  
Vol E93-C (5) ◽  
pp. 540-545 ◽  
Author(s):  
Dong Seup LEE ◽  
Hong-Seon YANG ◽  
Kwon-Chil KANG ◽  
Joung-Eob LEE ◽  
Jung Han LEE ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

scholarly journals A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Xiaoshi Jin ◽  
Yicheng Wang ◽  
Kailu Ma ◽  
Meile Wu ◽  
Xi Liu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Structural Parameters ◽  
Cmos Integrated Circuits ◽  
Region Length ◽  
Internal Mechanism ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Switching Characteristics

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

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