Bias polarity-sensitive electrical failure characteristics of ZnSe nanowire in metal–semiconductor–metal nanostructure

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

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A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0419 ◽

2019 ◽

Author(s):

Rommel Estores ◽

Karo Vander Gucht

Keyword(s):

Fault Injection ◽

Fault Simulation ◽

Fault Localization ◽

Pattern Generation ◽

Test Coverage ◽

Actual Case ◽

Electrical Failure ◽

Starting Point ◽

Diagnostic Resolution ◽

Diagnosis Approach

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

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Case Study of Electro-Optical Probing Signal with High Signal-Noise Ratio

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0123 ◽

2019 ◽

Author(s):

Ryan Xiao ◽

William Wang ◽

Ang Li ◽

Shengqiu Xu ◽

Binghai Liu

Keyword(s):

Failure Mode ◽

High Signal ◽

Signal Noise ◽

Electrical Failure ◽

Current Path ◽

Probing Signal ◽

Optical Probing ◽

Noise Ratio ◽

Case Collection

Abstract With the development of semiconductor technology and the increment quantity of metal layers in past few years, backside EFA (Electrical Failure Analysis) technology has become the dominant method. In this paper, abnormally high Signal Noise Ratio (SNR) signal captured by Electro-Optical Probing (EOP)/Laser Voltage Probing (LVP) from backside is shown and the cause of these phenomena are studied. Based on the real case collection, two kinds of failure mode are summarized, and simulated experiments are performed. The results indicate that when a current path from power to ground is formed, the high SNR signal can be captured at the transistor which was on this current path. It is helpful of this consequence for FA to identify the failure mode by high SNR signal.

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Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1996p0141 ◽

1996 ◽

Author(s):

H. Sur ◽

S. Bothra ◽

Y. Strunk ◽

J. Hahn

Keyword(s):

Process Development ◽

Process Integration ◽

Wafer Level ◽

Electrical Failure ◽

Analysis Techniques ◽

Integration Approach ◽

Intermetal Dielectric ◽

Metallization Process ◽

Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

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Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2002p0771 ◽

2002 ◽

Author(s):

Hui Pan ◽

Thomas Gibson

Keyword(s):

Failure Analysis ◽

Focused Ion Beam ◽

Ion Beam ◽

Electrical Characterization ◽

Charge Pump ◽

Front Side ◽

Pump Failure ◽

Electrical Failure ◽

Optical Proximity Correction ◽

A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

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Experimental Study and Numerical Simulation for Explosion and Phenomena of RC Slabs

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.501-504.1096 ◽

2014 ◽

Vol 501-504 ◽

pp. 1096-1103

Author(s):

Hong Xiao Wu ◽

Hao Zhe Xing ◽

Zhi Fang Yan

Keyword(s):

Reinforced Concrete ◽

Impact Loading ◽

Loading Condition ◽

Damage Mechanism ◽

Failure Characteristics ◽

Explosion Pressure ◽

Concrete Plate ◽

Solid Models ◽

Calculation Results ◽

Rc Slabs

The blast impact dynamic experiment of reinforced concrete rectangular plate with simply supported boundary conditions was performed using explosion pressure simulator. With 3-D FEM software LS-DYNA, the separate solid models of concrete and steel were established and 3-D FEM dynamic analysis of the experiment process was carried out. Compared calculation results to experiment results synthetically, the damage mechanism and failure characteristics of reinforced concrete plate under explosion impact loading condition were got and it is also verified that the H-J-C model can approximately simulate the concrete properties well under explosion impact loading condition.

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