Influence of Interface Traps Density and Temperature Variation on the NBTI Effect in p-Type Junctionless Nanowire Transistors

2019 ◽

Vol 53 (2) ◽

pp. 241

Author(s):

М.Б. Шалимова ◽

Н.В. Сачук

Keyword(s):

Electric Fields ◽

Transmission Mechanism ◽

Interface Traps ◽

Power Dependence ◽

Trap Charge ◽

Insulator Film ◽

Current Transmission ◽

Capacitance Voltage ◽

Silicon And Germanium ◽

P Type

AbstractThe electrophysical characteristics of silicon and germanium MIS structures with an SmF_3 insulator film, as well as their degradation due to the effect of electric fields, although similar, have a number of specific features. The current-transmission mechanism in all studied structures is described by the power dependence. Interface traps form the charge of electrically active traps, which varies during capacitance–voltage measurements, and the charge of inactive traps, which remains invariable. This charge is negative on the n -Ge surface, and the corresponding charge on the n -type and p -type silicon surface is positive. The trap charge density in the bulk of samarium fluoride lies in the range from –0.2 × 10^–8 to 0.6 × 10^–8 C/cm^2 and is negligibly small when compared with the charge of interface traps in most cases.

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On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

Materials Science Forum ◽

10.4028/www.scientific.net/msf.527-529.1007 ◽

2006 ◽

Vol 527-529 ◽

pp. 1007-1010 ◽

Cited By ~ 7

Author(s):

Daniel B. Habersat ◽

Aivars J. Lelis ◽

G. Lopez ◽

J.M. McGarrity ◽

F. Barry McLean

Keyword(s):

Room Temperature ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Interface Traps ◽

Mos Capacitors ◽

Mos Devices ◽

Interface Charges ◽

Flatband Voltage ◽

Oxide Traps ◽

P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

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Performance investigation of p-type Ge- and Ge-Core/Si-Shell junctionless nanowire transistors

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2014.7021285 ◽

2014 ◽

Author(s):

Hao Xu ◽

Lei Sun ◽

Yi-Bo Zhang ◽

Jing-Wen Han ◽

Yi Wang ◽

...

Keyword(s):

Nanowire Transistors ◽

P Type

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Complex Band Structure Effects in k $\cdot$ p-Based Quantum Transport Simulations of p-Type Silicon Nanowire Transistors

IEEE Transactions on Electron Devices ◽

10.1109/ted.2018.2808842 ◽

2018 ◽

Vol 65 (4) ◽

pp. 1298-1302 ◽

Cited By ~ 1

Author(s):

Anne Ziegler ◽

Mathieu Luisier

Keyword(s):

Band Structure ◽

Quantum Transport ◽

Silicon Nanowire ◽

Nanowire Transistors ◽

Type Silicon ◽

P Type

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Flicker noise in N-type and P-type silicon nanowire transistors

2008 IEEE Silicon Nanoelectronics Workshop ◽

10.1109/snw.2008.5418460 ◽

2008 ◽

Cited By ~ 1

Author(s):

Seungwon Yang ◽

Younghwan Son ◽

Sung Dae Suk ◽

Dong-Won Kim ◽

Donggun Park ◽

...

Keyword(s):

Flicker Noise ◽

Silicon Nanowire ◽

Nanowire Transistors ◽

Type Silicon ◽

P Type

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Physical Insights on the Dynamic Response of SOI n- and p-Type Junc-tionless Nanowire Transistors

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v13i1.17 ◽

2018 ◽

Vol 13 (1) ◽

pp. 1-7

Author(s):

Rodrigo Trevisoli Doria ◽

Renan Trevisoli ◽

Michelly De Souza ◽

Marcelo Antonio Pavanello

Keyword(s):

Dynamic Response ◽

Dynamic Behavior ◽

Transit Time ◽

Switching Time ◽

Series Resistance ◽

Inversion Mode ◽

Maximum Oscillation Frequency ◽

Nanowire Transistors ◽

P Type ◽

First Time

This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p- and n-type Junctionless Nanowire Transistors. The dynamic behavior evaluation will be carried out through the analysis of the limitation imposed by such parameters on the maximum oscillation frequency (fmax). In the sequence, it will be shown the impacts of fmax and the carriers’ transit time on the minimum switching time presented by JNTs. It has been observed that Junctionless devices present lower fmax than inversion mode transistors of similar dimensions due to higher resistance and lower transconductance. However, the intrinsic capacitances of such devices are smaller than the inversion mode ones, which compensates part of the degradation on fmax caused by the other parameters. Besides that, it is shown that transit time can be important on the dynamic behavior of long devices, but plays a negligible role in shorter ones.

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