Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

2010 ◽  
Vol 49 (9) ◽  
pp. 094102 ◽  
Author(s):  
Heesang Kim ◽  
Byoungchan Oh ◽  
Kyungdo Kim ◽  
Seon-Yong Cha ◽  
Jae-Goan Jeong ◽  
...  
Keyword(s):  
Leakage Current ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Random Telegraph Signal ◽  
Saddle Type

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Strong Electric Field ◽  
Memory Performance ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Access Memory ◽  
Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices

1999 ◽  
Vol 46 (5) ◽  
pp. 940-946 ◽  
Author(s):  
Daewon Ha ◽  
Changhyun Cho ◽  
Dongwon Shin ◽  
Gwan-Hyeob Koh ◽  
Tae-Young Chung ◽  
...  
Keyword(s):  
Leakage Current ◽  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Memory Devices ◽  
Access Memory

scholarly journals Analysis of Leakage Current of HfO2/TaOx-Based 3-D Vertical Resistive Random Access Memory Array

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 614
Author(s):  
Zhisheng Chen ◽  
Renjun Song ◽  
Qiang Huo ◽  
Qirui Ren ◽  
Chenrui Zhang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Current Model ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Storage ◽  
Access Memory ◽  
Leakage Currents ◽  
The Impact

Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. However, the leakage current (LC) of the 3-D VRRAM array is a concern as well. Excess leakage currents not only reduce the read/write tolerance and liability of the memory cell but also increase the power consumption of the entire array. In this article, a 3-D circuit HSPICE simulation is used to analyze the impact of the array size and operation voltage on the leakage current in the 3-D VRRAM architecture. The simulation results show that rapidly increasing leakage currents significantly affect the size of 3-D layers. A high read voltage is profitable for enhancing the read margin. However, the leakage current also increases. Alleviating this conflict requires a trade-off when setting the input voltage. A method to improve the array read/write efficiency is proposed by analyzing the influence of the multi-bit operations on the overall leakage current. Finally, this paper explores different methods to reduce the leakage current in the 3-D VRRAM array. The leakage current model proposed in this paper provides an efficient performance prediction solution for the initial design of 3-D VRRAM arrays.

Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure

2007 ◽  
Vol 46 (4B) ◽  
pp. 2143-2147 ◽  
Author(s):  
Hoon Jeong ◽  
Yeun Seung Lee ◽  
Sangwoo Kang ◽  
Il Han Park ◽  
Woo Young Choi ◽  
...  
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Gate Structure ◽  
Surrounding Gate
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