An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Change of the Characterization Techniques as Progress of CuInSe2-Based Thin-Film PV Technology

2012 ◽  
Vol 725 ◽  
pp. 165-170
Author(s):  
Katsumi Kushiya ◽  
Hiroki Sugimoto ◽  
Yoshiyuki Chiba ◽  
Yoshiaki Tanaka ◽  
Hideki Hakuma
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
Limited Information ◽  
Large Area ◽  
Area Efficiency ◽  
Characterization Techniques ◽  
First Time ◽  
Film Form ◽  
Comprehensive Characterization

In the CuInSe2(CIS)-based thin-film PV technology, various characterization techniques have been applied to measure the composition, crystal structure, depth profile and defect chemistry and so on, since Boeing Aerospace, for the first time, has come to the 10 % milestone in a thin-film form in 1980 by fabricating a very small single cell with top grids. More advanced and comprehensive characterization techniques are being applied after over 18 % total-area efficiency was consistently achieved employing the “three stage method”, which was developed by National Renewable Energy Laboratory (NREL). Comparing to the CIS-based absorber, there are not so many researches to investigate the absorber/buffer interface because the buffer is too thin to analyse separately and precisely and there are quite limited information on reaction pathways and composition of the buffer layer. However, in order to achieve the aperture-area efficiency of over 18 % on over 800cm2-sized large-area integrated circuits, it is remarkably important how to enhance the quality of absorber/buffer interface. Therefore, analytical works to understand how to improve the FF should tend to be more and more important.

Precipitation in silicon-on-insulator material during high- temperature annealing

1987 ◽  
Vol 45 ◽  
pp. 254-255
Author(s):  
S. J. Krause ◽  
C. O. Jung ◽  
S.R. Wilson
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Annealing Time ◽  
High Speed ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Precipitate Size ◽  
High Dose ◽  
High Temperature Annealing ◽  
Implantation Energy

Silicon-on-insulator (SOI) structure by high dose oxygen implantation (SIMOX) has excellent potential for use in radiation hardened and high speed integrated circuits. Device fabrication in SIMOX requires a high quality superficial Si layer above the buried oxide layer. Previously we reported on the effect of heater temperature, background doping, and annealing cycle on precipitate size, density, and location in the superficial Si layer. Precipitates were not eliminated with our processing conditions, but various authors have recently reported that high temperature annealing of SIMOX, from 1250°C to 1405°C, eliminates virtually all precipitates in the superficial Si layer. However, in those studies there were significant differences in implantation energy and dose and also annealing time and temperature. Here we are reporting on the effect of annealing time and temperature on the formation and changes in precipitates.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Die Bonding Issues on Silicon Carbide Diodes

2006 ◽  
Vol 527-529 ◽  
pp. 875-878 ◽  
Author(s):  
Seung Yong Lee ◽  
Jang Sub Lee ◽  
Tae Hong Kim ◽  
Sung Yong Choi ◽  
Hak Jong Kim ◽  
...  
Keyword(s):  
Shear Test ◽  
Vertical Structure ◽  
Optical Microscope ◽  
Device Fabrication ◽  
Cleaning Process ◽  
X Ray ◽  
The Third ◽  
Bottom Side ◽  
Die Bonding

We report on the die bonding processes and how the surface roughness and metallization schemes affect the processes of die bonding in 4H-SiC device fabrication using a soldering test and die shear test (DST) with differently prepared 4H-SiC samples. The first set of samples (FZ#1 and FZ#2) was capped with sequentially evaporated Ti and Au on an annealed Ni layer. The second set of samples (FZ#3 and FZ#4) and the third set of samples (FZ#5 and FZ#6) were prepared by 4μm-thick Au electroplating on an annealed Ni layer and an un-annealed Ni layer, respectively. The quality of the soldering, such as the solder coverage, void, and adhesion, was characterized by optical microscope, X-ray microprobe, and DST. We found that the samples (FZ#4 and FZ#6) deposited by Au electroplating on C-face (bottom-side) 4H-SiC provided a satisfactory result for the tests of solder coverage, void, and DST and also realized the cleaning process prior to the electroplating and soldering was the most crucial in the die packaging processes of vertical structure devices. The void fraction measured by X-ray microprobe for the samples, FZ#4 and FZ#6 was 2.2% (average for 5 samples) and 0.8% (average for 3 samples), respectively.

Free Vibration Analysis for Thin Wire of Modern Wiresaw Between Sliced Wafers in Wafer Manufacturing Processes

2000 ◽  
Author(s):  
Songbin Wei ◽  
Imin Kao
Keyword(s):  
High Speed ◽  
Free Vibration Analysis ◽  
Equation Of Motion ◽  
Manufacturing Processes ◽  
Thin Wire ◽  
Wire Vibration ◽  
The Wire ◽  
The Impact ◽  
Wafer Manufacturing ◽  
Impact Problem

Abstract In wiresaw manufacturing process where thin wire moving at high speed is pushed onto ingot to produce slices of wafer, the wire is constrained by two wafer walls as it slices into the ingot. In this paper, we investigate the vibration of such wire under the constraints of wafer walls. To address this problem, the model for wire vibration with impact to wafer walls is developed. The equation of motion is discretized using the Galerkin’s method. The principle of impulse and momentum is utilized to solve the impact problem. The results of analysis and simulation indicate that the response under a pointwise sinusoidal excitation is neither periodical nor symmetric with respect to the horizontal axis, due to the excitation from the impact. The wire vibration behavior is affected dramatically by the wafer wall constraints.

Iron tablets: disintegration tests

1965 ◽  
Vol 3 (1) ◽  
pp. 1-2
Keyword(s):  
Small Intestine ◽  
Manufacturing Processes ◽  
The Past

Iron is mainly absorbed in the upper small intestine and it is therefore important that iron tablets should not take too long to disintegrate. In the past most physicians were aware that some iron tablets were ineffective because they failed to disintegrate. Since then manufacturing processes have improved, but there is still no published information on the disintegration of iron tablets: indeed, this country still lacks a comprehensive scheme for supervising and checking the quality of drugs.1

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