Precipitation in silicon-on-insulator material during high- temperature annealing

1987 ◽  
Vol 45 ◽  
pp. 254-255
Author(s):  
S. J. Krause ◽  
C. O. Jung ◽  
S.R. Wilson
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Annealing Time ◽  
High Speed ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Precipitate Size ◽  
High Dose ◽  
High Temperature Annealing ◽  
Implantation Energy

Silicon-on-insulator (SOI) structure by high dose oxygen implantation (SIMOX) has excellent potential for use in radiation hardened and high speed integrated circuits. Device fabrication in SIMOX requires a high quality superficial Si layer above the buried oxide layer. Previously we reported on the effect of heater temperature, background doping, and annealing cycle on precipitate size, density, and location in the superficial Si layer. Precipitates were not eliminated with our processing conditions, but various authors have recently reported that high temperature annealing of SIMOX, from 1250°C to 1405°C, eliminates virtually all precipitates in the superficial Si layer. However, in those studies there were significant differences in implantation energy and dose and also annealing time and temperature. Here we are reporting on the effect of annealing time and temperature on the formation and changes in precipitates.

Evolution and Future Trends of SIMOX Material

MRS Bulletin ◽  
1998 ◽  
Vol 23 (12) ◽  
pp. 25-29 ◽  
Author(s):  
Steve Krause ◽  
Maria Anc ◽  
Peter Roitman
Keyword(s):  
High Temperature ◽  
Low Power ◽  
High Speed ◽  
New Technologies ◽  
Low Voltage ◽  
Semiconductor Industry ◽  
High Energy ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing

Oxygen-implanted silicon-on-insulator (SOI) material, or SIMOX (separation by implantation of oxygen), is another chapter in the continuing development of new material technologies for use by the semiconductor industry. Building integrated circuits (ICs) in a thin layer of crystalline silicon on a layer of silicon oxide on a silicon substrate has benefits for radiationhard, high-temperature, high-speed, low-voltage, and low-power operation, and for future device designs. Historically the first interest in SIMOX was for radiation-hard electronics for space, but the major application of interest currently is low-power, high-speed, portable electronics. Silicon-on-insulator also avoids the disadvantage of a completely different substrate such as sapphire or gallium arsenide. Formation of a buried-oxide (BOX) layer by high-energy, high-dose, oxygen ion implantation has the advantage that the ion-implant dose can be made extremely precise and extremely uniform. However the silicon and oxide layers are highly damaged after the implant, so high-temperature annealing sequences are required to restore devicequality material. In fact SIMOX process development necessitated the development of new technologies for high-dose implantation and high-temperature annealing.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

High-Quality SOI by Oxygen Implantation into Silicon

1987 ◽  
Vol 93 ◽  
Author(s):  
A. H. van Ommen ◽  
H. J. Ligthart ◽  
J. Politiek ◽  
M. P. A. Viegers
Keyword(s):  
High Temperature ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Quality ◽  
Cubic Symmetry ◽  
Buried Oxide ◽  
Simple Cubic ◽  
Precipitate Growth

ABSTRACTHigh quality Silicon-On-Insulator, with a dislocation density lower than 105cm−2, has been formed by high temperature annealing of high-dose oxygen implanted silicon. In the as-implanted state, oxygen was found to form precipitates in the top silicon film. In the upper region these precipitates were found to order into a superlattice of simple cubic symmetry. Near the interface with the buried oxide film the precipitates are larger and no ordering occurs in that region. Contrary to implants without precipitate ordering where dislocations are observed across the entire layer thickness of the top silicon film, dislocations are now only found near the buried oxide. The precipitate ordering appears to prevent the dislocations to climb to the surface. High temperature annealing results in precipitate growth in this region whereas they dissolve elsewhere. These growing precipitates pin the dislocations and elimination of precipitates and dislocations occurs simultaneously, resulting in good quality SOI material.

Origin of the defect structures in oxygen-implanted silicon-on-insulator material

1993 ◽  
Vol 51 ◽  
pp. 1108-1109
Author(s):  
D. Venables ◽  
S.J. Krause ◽  
J.D. Lee ◽  
J.C. Park ◽  
P. Roitman
Keyword(s):  
High Temperature ◽  
High Speed ◽  
Silicon Layer ◽  
Dark Field ◽  
Silicon On Insulator ◽  
High Dose ◽  
Defect Structures ◽  
Plan View ◽  
High Temperature Anneal ◽  
Single Oxygen

Silicon-on-insulator material fabricated by high-dose oxygen implantation (known as SIMOX) has been used for high speed and radiation hard devices and is under consideration for use in low power applications. However, a continuing problem has been crystalline defects in the top silicon layer. SIMOX is fabricated by two distinct methods: a single oxygen implant to a dose of 1.8×l018 cm-2 followed by a high-temperature anneal (≥1300°C, 4-6 hr) or by multiple lower dose implants (∼6×l017 cm-2) with high-temperature anneals after each implant. To date, there has been no systematic comparison of the defect structures produced by these two fabrication methods. Therefore, we have compared the defect structure and densities in multiple vs. single implant wafers. In this paper we describe the origin and characteristics of the defect structures in SIMOX and show how their densities are controlled by the processing method and conditions.Silicon (100) wafers were implanted in a high current implanter at ∼620°C to doses of 1.8×l018 or 0.6/0.6/0.6×l018 cm-2 and annealed at 1325°C, 4 hr in 0.5% or 5% O2 in Ar. Cross-section (XTEM) and plan-view (PTEM) samples were studied with bright field and weak beam dark field techniques in a transmission electron microscope operating at 200 keV.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

Evening Panel Session (November 16, 1983) Soi Technologies for Integrated Circuits

1983 ◽  
Vol 23 ◽  
Author(s):  
John C. C. Fan ◽  
Y. Akasaka ◽  
G. W. Cullen ◽  
J. F. Gibbons ◽  
C. Hill ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Density ◽  
Silicon On Insulator ◽  
Panel Session ◽  
Near Term

There are a number of viable approaches to silicon-on-insulator (SOI) technologies, and the panel session has assembled a number of leaders in the SOI community for their views of “SOI Technologies for Integrated Circuits.” Their viewpoints, shown in tabulated form, were presented for general discussion in the session which was attended by about 150 people. Although SOI technologies are useful for many applications, most of the panelists agreed that the most appropriate near-term applications are for high-speed, high-density integrated circuits. Various SOI technologies, including silicon-on-sapphire (SOS), are currently in the running, but the majority of the panelists felt that for SOI technologies to be widely adopted, SOI must be available as a proven manufactured product within two to three years.

On the Formation of Intrinsic Defects in 4H-SiC by High Temperature Annealing Steps

2012 ◽  
Vol 717-720 ◽  
pp. 247-250 ◽  
Author(s):  
Bernd Zippelius ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
High Temperature ◽  
Carrier Lifetime ◽  
Growth Conditions ◽  
Device Fabrication ◽  
Defect Concentration ◽  
Epitaxial Layers ◽  
High Temperature Annealing ◽  
Intrinsic Defects ◽  
Initial Defect ◽  
The Impact

In this paper the impact of high temperature annealing on the formation of intrinsic defects in 4H-SiC such as Z1/2 and EH6/7 was examined. Therefore, three epitaxial layers with various initial concentrations of the Z1/2- and EH6/7-centers (1011 – 1013 cm-3) were investigated. It turns out that depending on the initial defect concentration the high temperature annealing leads to a monotone increase of the Z1/2- and EH6/7-concentration in a temperature range from 1600 to 1750°C. For a defined temperature above these values, the resulting defect concentration is independent of the sample’s initial values. Beside the growth conditions themselves such as C/Si ratio the thermal post-growth processing has a severe impact on the carrier lifetime which must be taken into account during device fabrication.

scholarly journals High Temperature Silicon Integrated Circuits and Passive Components for Commercial and Military Applications

1998 ◽  
Author(s):  
Richard R. Grzybowski ◽  
Ben Gingrich
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Elevated Temperatures ◽  
Silicon On Insulator ◽  
Passive Component ◽  
Oil Well ◽  
Automotive Electronics ◽  
Passive Components ◽  
Silicon Integrated Circuits

Advances in silicon-on-insulator (SOI) integrated circuit technology and the steady development of wider band gap semiconductors like silicon carbide are enabling the practical deployment of high temperature electronics. High temperature civilian and military electronics applications include distributed controls for aircraft, automotive electronics, electric vehicles and instrumentation for geothermal wells, oil well logging and nuclear reactors. While integrated circuits are key to the realization of complete high temperature electronic systems, passive components including resistors, capacitors, magnetics and crystals are also required. This paper will present characterization data obtained from a number of silicon high temperature integrated evaluated over a range of elevated temperatures and aged at a selected high temperature. This paper will also present a representative cross section of high temperature passive component characterization data for device types needed by many applications. Device types represented will include both small signal and power resistors and capacitors. Specific problems encountered with the employment of these devices in harsh environments will be discussed for each family of components. The goal in presenting this information is to demonstrate the viability of a significant number of commercially available silicon integrated circuits and passive components that operate at elevated temperatures as well as to encourage component suppliers to continue to optimize a selection of their product offerings for operation at higher temperatures. In addition, systems designers will be encouraged to view this information with an eye toward the conception and implementation of reliable and affordable high temperature systems.

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