A High-Performance RSA Coprocessor Based on Half-Carry-Save and Dual-Core MAC Architecture

2018 ◽  
Vol 27 (1) ◽  
pp. 70-75
Author(s):  
Yanyu Ding ◽  
Jianguo Hu ◽  
Deming Wang ◽  
Hongzhou Tan
Keyword(s):  
High Performance ◽  
Dual Core

Photovoltaic Cell Test System Based on Dual-Core Processors

2011 ◽  
Vol 121-126 ◽  
pp. 4229-4233
Author(s):  
Ping Chuan Zhang ◽  
Yun Long Kong ◽  
Hang Sen Zhang
Keyword(s):  
High Performance ◽  
Fill Factor ◽  
Photovoltaic Cells ◽  
Photovoltaic Cell ◽  
Test System ◽  
Photoelectric Conversion Efficiency ◽  
Photoelectric Conversion ◽  
Data Processing Center ◽  
Cell Test ◽  
Dual Core

This paper design an intelligent photovoltaic cell test system. The high performance dual-core 16bits SPCE061A microprocessors are used as control and data processing center. The powerful data operation ability of SPCE061A makes it to carry out software filter for measured data and enhances testing precision. the experiments demonstrated the test system can measure the characteristic parameters of photovoltaic cells: open voltage, current, the fill factor and photoelectric conversion efficiency, draw photovoltaic cells I-V curve, find the best working points , and also have the characteristics of miniaturization and intelligent.

Implementation and Optimization of Tracking System on Dual-DSP

2011 ◽  
Vol 58-60 ◽  
pp. 2231-2236
Author(s):  
Qiang Wu ◽  
Shi Dong Li ◽  
Le Gong Sun ◽  
Yu Fei Zhou
Keyword(s):  
Real Time ◽  
High Performance ◽  
Tracking System ◽  
Tracking Algorithm ◽  
Input And Output ◽  
Dual Core ◽  
Strong Ability ◽  
Low Consumption

The paper provides a solution of tracking system on dual-DSP(ADSP-BF561, ADP-BF548), and gives the method of implementation and optimization. The system implements the complex tracking algorithm in real time on the high-performance dual-core ADSP -BF561. The multimedia processor ADSP-BF548，which has integrated a pixel composer and many interfaces internally, is used to control the entire operating of the system and complete the task of input and output flexibly. With the help of the code and decode chips ADV7181 and ADV7171, which have strong ability of adaption to varieties of video formats, the system has the features of easy- expansibility, strong adaption, stabilize, function, small size and low consumption.

scholarly journals MnO2-Coated Dual Core–Shell Spindle-Like Nanorods for Improved Capacity Retention of Lithium–Sulfur Batteries

2020 ◽  
Vol 4 (2) ◽  
pp. 42 ◽  
Author(s):  
Hamza Dunya ◽  
Maziar Ashuri ◽  
Dana Alramahi ◽  
Zheng Yue ◽  
Kamil Kucuk ◽  
...  
Keyword(s):  
High Performance ◽  
Synergistic Effects ◽  
Coulombic Efficiency ◽  
Rate Capability ◽  
Core Shell ◽  
Shuttle Effect ◽  
Lithium Sulfur Batteries ◽  
Hollow Carbon ◽  
Dual Core ◽  
Lithium Sulfur

The emerging need for high-performance lithium–sulfur batteries has motivated many researchers to investigate different designs. However, the polysulfide shuttle effect, which is the result of dissolution of many intermediate polysulfides in electrolyte, has still remained unsolved. In this study, we have designed a sulfur-filled dual core–shell spindle-like nanorod structure coated with manganese oxide (S@HCNR@MnO2) to achieve a high-performance cathode for lithium–sulfur batteries. The cathode showed an initial discharge capacity of 1661 mA h g−1 with 80% retention of capacity over 70 cycles at a 0.2C rate. Furthermore, compared with the nanorods without any coating (S@HCNR), the MnO2-coated material displayed superior rate capability, cycling stability, and Coulombic efficiency. The synergistic effects of the nitrogen-doped hollow carbon host and the MnO2 second shell are responsible for the improved electrochemical performance of this nanostructure.

scholarly journals Multicore-Processor Based Software-Defined Communication/Network Platform for Underwater Internet of Things

Sensors ◽  
2019 ◽  
Vol 19 (23) ◽  
pp. 5168 ◽  
Author(s):  
Chaohui Luo ◽  
Biyun Ma ◽  
Fangjiong Chen ◽  
Quansheng Guan ◽  
Hua Yu ◽  
...  
Keyword(s):  
High Performance ◽  
Physical Layer ◽  
Network Simulator ◽  
Multicore Processor ◽  
Acoustic Channel ◽  
Important Research Topic ◽  
Network Platform ◽  
Reconfigurable Platform ◽  
Networking Protocols ◽  
Dual Core

Software-defined acoustic modems (SDAMs) for underwater communication and networking have been an important research topic due to their flexibility and programmability. In this paper, we propose a reconfigurable platform for SDAMs based on the TI AM5728 processor, which integrates dual-core ARM Cortex-A15 CPUs and two TI C66x DSP cores. The signal processing and A/D, D/A for physical-layer communication are implemented in the DSP cores. The networking protocols and the application programs are implemented in the ARM cores. The proposed platform has the following characteristics: (1) Due to the high-performance dual-ARM cores, the whole NS3 network simulator can be run in the ARM cores. Network protocols developed in a software simulation platform (e.g., NS3 platform) can be seamlessly migrated to a hardware platform without modification. (2) A new physical-layer module associated with real acoustic channel is developed, such that a data packet generated from the application layer will be transmitted through a real acoustic channel. The results of networking experiments with five nodes are presented to demonstrate the effectiveness of the proposed platform.

ARM Dual Core Product Demonstration with 2.5D Through-Silicon-Via (TSV)

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000665-000693
Author(s):  
Michael Kelly ◽  
Rick Reed
Keyword(s):  
High Speed ◽  
High Performance ◽  
Functional System ◽  
Process Technology ◽  
Test Vehicle ◽  
Through Silicon Via ◽  
The Real Estate ◽  
Key Factor ◽  
And Performance ◽  
Dual Core

Through-silicon-via (TSV) package construction offers several silicon integration advantages that are being validated by leading technology providers. This paper will describe a System in Package (SiP) design utilizing two functional system-on-chip (SoC) ARM dual-core Cortex-A9 processors connected across a 2.5D silicon interposer. The test vehicle was designed to demonstrate high speed and high bandwidth communication between multiple chips. The two logic chips were designed by Open Silicon, Inc. and fabricated by GLOBALFOUNDRIES on their 28nm-SLP (Super Low Power) process technology. GLOBALFOUNDRIES also fabricated the 2.5D interposer using their 65nm manufacturing flow. Amkor Technology provided the final assembly utilizing advanced TSV packaging technologies such as copper pillar bumping and mass reflow bonding. This is a pivotal demonstration of the heterogeneous die integration approach. A silicon process node or package interconnect density can either preserve or limit inter-chip communication when comparing SoC versus SiP approaches. Connecting two dual-core Cortex-A9 processors within a single package illustrated the expansion of function through multiple die. The test vehicle also implies that a large IC can be re-architected into smaller constituents to increase yield or design flexibility. By utilizing the best technology node for price and performance, 2.5D packaging can lower overall system cost of ownership or conversely, can expand overall performance through multiple high performance ICs. Chip designers are facing increased complexity and higher costs in order to move to smaller IC geometries and the adoption of 2.5D TSV technology will increase the options of construction (one vs. multiple die/SoCs). Having the flexibility to design with one or multiple die while maintaining high performance levels can offset the real estate costs of advanced nodes, permit silicon die reuse, improve yield and decrease overall product risk. The designer must choose the most appropriate silicon and assembly processes that satisfy the needs of each of the major functions in the overall system. Amkor's assembly process for this key product construction has been demonstrated on a range of products for the communications, graphics and the mobile markets. Process flexibility has been a key factor in addressing different markets and package complexity.

scholarly journals Multi–GPU Implementation of Machine Learning Algorithm using CUDA and OpenCL

2016 ◽  
Vol 5 (2) ◽  
pp. 101 ◽  
Author(s):  
Jan Masek ◽  
Radim Burget ◽  
Lukas Povoda ◽  
Malay Kishore Dutta
Keyword(s):  
High Performance ◽  
Nearest Neighbor ◽  
Learning Algorithm ◽  
Data Sets ◽  
K Nearest Neighbor ◽  
Graphic Processing Units ◽  
Speed Up ◽  
Performance Of Algorithm ◽  
Dual Core ◽  
Gpu Implementation

Using modern Graphic Processing Units (GPUs) becomes very useful for computing complex and time consuming processes. GPUs provide high–performance computation capabilities with a good price. This paper deals with a multi–GPU OpenCL and CUDA implementations of k–Nearest Neighbor (k–NN) algorithm. This work compares performances of OpenCLand CUDA implementations where each of them is suitable for different number of used attributes. The proposed CUDA algorithm achieves acceleration up to 880x in comparison witha single thread CPU version. The common k-NN was modified to be faster when the lower number of k neighbors is set. The performance of algorithm was verified with two GPUs dual-core NVIDIA GeForce GTX 690 and CPU Intel Core i7 3770 with 4.1 GHz frequency. The results of speed up were measured for one GPU, two GPUs, three and four GPUs. We performed several tests with data sets containing up to 4 million elements with various number of attributes.

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