Analysis of peak to average power reduction technique in presence of nonlinear distortion

2016 ◽  
Author(s):  
S.A. Kulkarni ◽  
B.K. Mishra
Keyword(s):  
Nonlinear Distortion ◽  
Average Power ◽  
Power Reduction ◽  
Reduction Technique

scholarly journals PAPR Reduction in UFMC for 5G Cellular Systems

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1404
Author(s):  
Mohammed I. Al-Rayif ◽  
Hussein E. Seleem ◽  
Amr M. Ragheb ◽  
Saleh A. Alshebeili
Keyword(s):  
Nonlinear Distortion ◽  
Average Power ◽  
Reduction Technique ◽  
Cellular Systems ◽  
Papr Reduction ◽  
Error Vector Magnitude ◽  
Carrier System ◽  
Inverse Fast Fourier Transform ◽  
Selective Mapping ◽  
Vector Magnitude

Universal filtered multi-carrier (UFMC) is a potential multi-carrier system for future cellular networks. UFMC provides low latency, frequency offset robustness, and reduced out-of-band (OOB) emission that results in better spectral efficiency. However, UFMC suffers from the problem of high peak-to-average power ratio (PAPR), which might impact the function of high power amplifiers causing a nonlinear distortion. We propose a comparative probabilistic PAPR reduction technique, called the decomposed selective mapping approach, to alleviate PAPR in UFMC systems. The concept of this proposal depends on decomposing the complex symbol into real and imaginary parts, and then converting each part to a number of different phase vectors prior to the inverse fast Fourier transform (IFFT) operation. The IFFT copy, which introduces the lowest PAPR, is considered for transmission. Results obtained using theoretical analysis and simulations show that the proposed approach can significantly enhance the performance of the UFMC system in terms of PAPR reduction. Besides, it maintains the OOB emission with candidate bit error rate and error vector magnitude performances.

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

Sign in / Sign up

Export Citation Format

Share Document