Discretely tuned RF-MEMS bandstop filter with wide tuning range and uniform high rejection

2012 ◽  
Vol 48 (17) ◽  
pp. 1065-1067 ◽  
Author(s):  
I. Llamas-Garro ◽  
S. Colpo ◽  
L. Pradell ◽  
F. Giacomozzi ◽  
Z. Brito-Brito
2010 ◽  
Vol 46 (11) ◽  
pp. 771 ◽  
Author(s):  
Z.P. Wang ◽  
J. Kelly ◽  
P.S. Hall

2019 ◽  
Vol 55 (16) ◽  
pp. 910-912 ◽  
Author(s):  
Qun Li ◽  
Xiong Chen ◽  
Tao Yang

2011 ◽  
Vol 483 ◽  
pp. 132-136
Author(s):  
Yuan Wei Yu ◽  
J. Zhu ◽  
Yi Shi ◽  
Jian Yu

This paper presents a bandpass switchable filter for 6–11GHz applications which is housed in a machined aluminum chassis. The circuit consists of three fixed interdigital microstrip filters and two single-pole triple-throw (SP3T) microelectromechanical systems (MEMS) switching networks achieved by the individual series-shunt MEMS switch chips. A tuning range of 36.6% was achieved from 6.7 to 9.7 GHz with a fractional bandwidth of 21.1±2.7%, with low mid-band insertion loss ranging from 2.6 dB to 3.0 dB. Rejection is below -50 dB in most cases and skirt slopes are more than 50 dB/GHz at both lower and higher stopband.


PIERS Online ◽  
2008 ◽  
Vol 4 (4) ◽  
pp. 433-436 ◽  
Author(s):  
Yaping Liang ◽  
Calvin W. Domier ◽  
Neville C. Luhmann, Jr.

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1382
Author(s):  
Xiaoying Deng ◽  
Huazhang Li ◽  
Mingcheng Zhu

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.


2020 ◽  
Vol 98 ◽  
pp. 104752 ◽  
Author(s):  
M. Maiti ◽  
A. Majumder ◽  
S. Chakrabartty ◽  
H. Song ◽  
B.K. Bhattacharyya

1997 ◽  
Vol 45 (12) ◽  
pp. 2436-2443 ◽  
Author(s):  
K. Kamogawa ◽  
K. Nishikawa ◽  
C. Yamaguchi ◽  
M. Hirano ◽  
I. Toyoda ◽  
...  

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