scholarly journals 4.5kV FRD Development for high current power modules

2018 ◽  
Vol 232 ◽  
pp. 04048
Author(s):  
Jiang Liu ◽  
Yueyang Liu ◽  
Rui Jin ◽  
Feng He ◽  
Shaohua Dong ◽  
...  

A 4.5kV/100A FRD was designed by simulation, which had optimized carrier density distribute cell and ruggedness terminal. The cell was composed of P-body/N-sub/N+ layers, when the P-body doping concentration is lower, the carrier density distribution on the P-body/N-sub is lower; when carrier density di stribution on the P-body/N-sub side is lower than that on the N-sub/N+ side, the FRD has soft recovery but bad surge-current capability. So the P-body doping concentration needs trade-off consideration. Lifetime control technology was also used to optimize the carrier density distribution and trade-off characteristics. The terminal has high breakdown voltage, low electric field and large process window, which means more ruggedness and high reliability. The experiment results show that the design chip and competitor chip has nearly the same trade-off characteristics, the design chip has larger dynamic loss but lower static loss. The design chip has high surge current, the surge current is 13 times as much as the rate current.

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001918-001947 ◽  
Author(s):  
Lars Boettcher ◽  
S. Karaszkiewicz ◽  
D. Manessis ◽  
A. Ostmann

Packages and modules with embedded semiconductor dies are of interest for various application fields and power classes. First packages in the lower power range are available in volume production since almost six years. Recent developments focus on medium and higher power applications raging over 500W into the kW range. Different approaches are available to realize such packages and modules. This paper will give an overview and detailed description of the latest approaches for such embedded die structures. In common of all of these approaches, is the use of laminate based die embedding, which uses standard PCB manufacturing technologies. Main differences are the used base substrate, which can still be a ceramic (DBC), Cu leadframe or high current substrate. Examples for the different methods will be given. As the main part, this paper will describe concepts, which enable significant smaller form-factor of power electronics modules, thereby allowing for lower price, high reliability, capability of direct mounting on e.g. a motor so as to form one unit with the motor housing, wide switching frequency range (for large application field) and high power efficiency. The innovative character of this packaging concept is the idea to embed the power drive components (IGBTs, MOSFETs, diode) as thinned chips into epoxy-resin layer built-up and to realize large-area interconnections on both sides by direct copper plating the dies to form a conductor structure with lowest possible electrical impedance and to achieve an optimum heat removal. In this way a thin core is formed on a large panel format which is called Embedded Power Core. The paper will specifically highlight the first results on manufacturing an embedded power discrete package as an example of an embedded power core containing a thin rectifier diode. For module realization, the power cores are interconnected to insulated metal substrates (IMS) by the use of Ag sintering interconnection technologies for the final manufacturing of Power modules. The paper will elaborate on the sintering process for Power Core/IMS interconnections, the microscopically features of the sintered interfaces, and the lateral filling of the sintering gap with epoxy prepregs. Firstly, 500W power modules were manufactured using this approach. Reliability testing results, solder reflow testing, temperature cycling test and active power cycling, will be discussed in detail.


2016 ◽  
Vol 64 ◽  
pp. 434-439 ◽  
Author(s):  
J. Ortiz Gonzalez ◽  
A.M. Aliyu ◽  
O. Alatise ◽  
A. Castellazzi ◽  
L. Ran ◽  
...  

2021 ◽  
Author(s):  
Jiho Yoon ◽  
See-Hun Yang ◽  
Jae-Chun Jeon ◽  
Andrea Migliorini ◽  
Ilya Kostanovskiy ◽  
...  

Abstract The current induced manipulation of chiral spin textures is of great interest for both fundamental research and technological applications1–3. Of particular interest are magnetic non-volatile memories formed from synthetic antiferromagnetic racetracks in which chiral composite domain walls (DWs), that act as data bits, can be efficiently moved by current4. However, overcoming the trade-off between energy efficiency, namely a low threshold current density to move the domain walls, and high thermal stability, remains a major challenge for the development of integrated chips with high reliability and low power consumption. Here we show that chiral DWs5–7 in a synthetic antiferromagnet-ferromagnet lateral junction, formed by local plasma oxidation, are highly stable against large magnetic fields whilst the DWs can be efficiently moved across the junction by current. Our approach takes advantage of the locality of current-driven torque on the small volume of a chiral DW and the globality of field-torque in the energy landscape, thereby leading to fundamentally distinct energy barriers for motion and stability. We find that the threshold current can be further decreased by tilting the junction across the racetrack while not affecting the high DW stability. Furthermore, we demonstrate that chiral DWs can be robustly confined within a ferromagnet region sandwiched on both their sides by synthetic antiferromagnets and yet can be readily injected into these regions by current. Our findings break the aforementioned trade-off between efficiency and stability, allowing for diverse and versatile DW-based memory, and logic, and beyond.


Micron ◽  
2015 ◽  
Vol 79 ◽  
pp. 93-100 ◽  
Author(s):  
Grzegorz Wielgoszewski ◽  
Piotr Pałetko ◽  
Daniel Tomaszewski ◽  
Michał Zaborowski ◽  
Grzegorz Jóźwiak ◽  
...  

2005 ◽  
Vol 483-485 ◽  
pp. 829-832 ◽  
Author(s):  
Tetsuo Hatakeyama ◽  
Takatoshi Watanabe ◽  
Junji Senzaki ◽  
Makoto Kato ◽  
Kenji Fukuda ◽  
...  

This paper reports on the degradation of inversion channel mobility of SiC MOSFET caused by the increase of channel doping. SiC MOSFETs were fabricated on three wafers, the doping concentrations of the epitaxial layer of which were 16 10 2× cm-3 (sample A), 17 10 2× cm-3 (sample B) and 17 10 4× cm-3 (sample C). The field effect mobility sharply decreases as the doping concentration increases. Hall mobility measurements have been done to investigate the degradation of the mobility due to doping. The measurement of sample A shows that, as a consequence of the decrease of the free carrier density due to MOS interface traps, the Hall mobility is as much as a factor of ten higher than the field effect mobility. In contrast, in regard to the measurement of sample B and sample C, we encountered unstable Hall voltage and could not obtain reproducible results. This implies that such high-density traps are generated that a channel disappears in the higher-doping samples.


2011 ◽  
Vol 98 (22) ◽  
pp. 221110 ◽  
Author(s):  
R. Pagano ◽  
M. Ziegler ◽  
J. W. Tomm ◽  
I. Esquivias ◽  
J. M. G. Tijero ◽  
...  

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