scholarly journals Control of the threshold voltage of polyvinylpyrrolidone-coated SnO2 nanowire transistor using xenon flash light irradiation

AIP Advances ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 025304
Author(s):  
Youngsoo Kang ◽  
Sanghyun Ju
2021 ◽  
Author(s):  
Nipanka Bora

Abstract This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.


2021 ◽  
Vol 16 (2) ◽  
pp. 318-323
Author(s):  
S. Manikandan ◽  
P. Suveetha Dhanaselvam ◽  
M. Karthigai Pandian

A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along the device channel. Higher drain bias conditions leading to DIBL are reduced in the proposed structure by minimal variation of voltages owing to three different gate materials that maintain a steady field distribution along the channel. This model explicitly shows the impact of various criteria like drain bias voltage, gate bias voltage, thickness of the silicon layer, thickness of the oxide layer, and length of the channel on electrostatic potential and the deterioration of threshold voltage. The proposed analytical model is validated with TCAD simulations and it could be further extended to study the advanced electrical characteristics of the JL Triple Material CSG Silicon Nanowire Transistor.


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