A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime

2021 ◽  
pp. 1-20
Author(s):  
Vijay Kumar Sharma
Keyword(s):  
Digital Circuits ◽  
Leakage Reduction ◽  
Reduction Techniques

LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES

2011 ◽  
Vol 20 (01) ◽  
pp. 147-162 ◽  
Author(s):  
WEIQIANG ZHANG ◽  
LI SU ◽  
YU ZHANG ◽  
LINFENG LI ◽  
JIANPING HU
Keyword(s):  
Total Power ◽  
High Threshold ◽  
Leakage Currents ◽  
Flip Flop ◽  
Leakage Reduction ◽  
Low Leakage ◽  
Reduction Techniques ◽  
Low Threshold ◽  
Critical Paths ◽  
P Type

The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

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