scholarly journals Research on Silicon Wafer Manufacturing Process and Physical Properties Testing Using High-Purity Polysilicon

2021 ◽  
Vol 2083 (2) ◽  
pp. 022050
Author(s):  
Xiaoming Hu

Abstract The shape of a bare wafer is round, so it is called a wafer or a silicon wafer. It is the basis for the production of silicon semiconductor integrated circuits. The silicon wafer is cut from a large piece of semiconductor material silicon ingot. The high-purity polysilicon (its purity is up to 99.999999999%) is into a large single crystal, given the correct orientation and an appropriate amount of N-type or P-type doping, a silicon ingot is obtained through five-step crystal growth. Wafers (wafers) are then made from silicon ingots by more than eight processes. This paper investigates the single crystal silicon growth and wafer preparation process technology, and finally discusses the evolution of wafer size growth and changes in the development of the semiconductor industry chain.

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 429
Author(s):  
Tengyun Liu ◽  
Peiqi Ge ◽  
Wenbo Bi

Lower warp is required for the single crystal silicon wafers sawn by a fixed diamond wire saw with the thinness of a silicon wafer. The residual stress in the surface layer of the silicon wafer is the primary reason for warp, which is generated by the phase transitions, elastic-plastic deformation, and non-uniform distribution of thermal energy during wire sawing. In this paper, an experiment of multi-wire sawing single crystal silicon is carried out, and the Raman spectra technique is used to detect the phase transitions and residual stress in the surface layer of the silicon wafers. Three different wire speeds are used to study the effect of wire speed on phase transition and residual stress of the silicon wafers. The experimental results indicate that amorphous silicon is generated during resin bonded diamond wire sawing, of which the Raman peaks are at 178.9 cm−1 and 468.5 cm−1. The ratio of the amorphous silicon surface area and the surface area of a single crystal silicon, and the depth of amorphous silicon layer increases with the increasing of wire speed. This indicates that more amorphous silicon is generated. There is both compressive stress and tensile stress on the surface layer of the silicon wafer. The residual tensile stress is between 0 and 200 MPa, and the compressive stress is between 0 and 300 MPa for the experimental results of this paper. Moreover, the residual stress increases with the increase of wire speed, indicating more amorphous silicon generated as well.


1986 ◽  
Vol 71 ◽  
Author(s):  
T I Kamins

AbstractThe electrical properties of polycrystalline silicon differ from those of single-crystal silicon because of the effect of grain boundaries. At low and moderate dopant concentrations, dopant segregation to and carrier trapping at grain boundaries reduces the conductivity of polysilicon markedly compared to that of similarly doped single-crystal silicon. Because the properties of moderately doped polysilicon are limited by grain boundaries, modifying the carrier traps at the grain boundaries by introducing hydrogen to saturate dangling bonds improves the conductivity of polysilicon and allows fabrication of moderate-quality transistors with their active regions in the polycrystalline films. Removing the grain boundaries by melting and recrystallization allows fabrication of high-quality transistors. When polysilicon is used as an interconnecting layer in integrated circuits, its limited conductivity can degrade circuit performance. At high dopant concentrations, the active carrier concentration is limited by the solid solubility of the dopant species in crystalline silicon. The current through oxide grown on polysilicon can be markedly higher than that on oxide of similar thickness grown on singlecrystal silicon because the rough surface of a polysilicon film enhances the local electric field in oxide thermally grown on it. Consequently, the structure must be controlled to obtain reproducible conduction through the oxide. The differences in the behavior of polysilicon and single-crystal silicon and the limited electrical conductivity in polysilicon are having a greater impact on integrated circuits as the feature size decreases and the number of devices on a chip increases in the VLSI era.


2012 ◽  
Vol 430-432 ◽  
pp. 404-407
Author(s):  
J.J. Li ◽  
C.W. Zhao ◽  
Y.M. Xing ◽  
Z.Y. Lv ◽  
Y.G. Du

The failure components made of silicon is an important issue in the electronic and nano-technological developments. A study on the near-crack-tip deformation of single-crystal silicon wafer under tensile load was presented. The strain formulas around the crack tip of mode I crack were deduced from linear elastic fracture mechanics. The strain fields around the crack tip were simulated and analyzed in detail.


1994 ◽  
Vol 2 (5) ◽  
pp. 8-8
Author(s):  
Mark W. Lund

A combination of electron microscope and x-ray spectrometer is a very powerful tool. Not only can one see a sample in great detail, but one can determine, and even map, the chemical elements. In Part 1, I discussed some of the basics of energy dispersive x-ray spectroscopy (EDS or EDX). The heart of the spectrometer is a small piece of single crystal silicon about the size and shape of a shirt button, and about twice as thick. It has been selected for high purity, and then lithium drifted to compensate the remaining impurities.The lithium is carefully drifted into the crystal button in order to exactly compensate the impurities in the crystal that would create leakage current. This is done at about 60° C under an electric field. It is then evaluated and re-drifted for a final clean up of any uncompensated impurity atoms that remain.


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