System-on-chip integrated circuit technology applications on the DIII-D tokamak for multi-field measurements

2022 ◽  
Vol 17 (01) ◽  
pp. C01013
Author(s):  
Y. Zheng ◽  
G.Y. Yu ◽  
J. Chen ◽  
Y. Chen ◽  
Y.L. Zhu ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Measurement Data ◽  
Field Measurements ◽  
System On Chip ◽  
Fusion Plasma ◽  
V Band ◽  
Technology Applications ◽  
Dimensional Measurements ◽  
On Chip ◽  
Circuit Technology

Abstract Several mm-wave diagnostics on the DIII-D tokamak provide multi-scale and multi-dimensional measurements of plasma profile evolution and turbulence fluctuations. Mm-wave fusion plasma diagnostics that adopt system-on-chip integrated circuit technology can provide better space utilization, flexible installation, and improved sensitivity. In order to further extend this technology for additional fusion facilities with a higher toroidal magnetic field, V-band (55–75 GHz) and F-band (90–140 GHz) chips for Microwave Imaging Reflectometer (MIR) and Electron Cyclotron Emission Imaging (ECEI) instruments are developed and tested in the Davis Millimeter Wave Research Center (DMRC). Current measurement data show that correlation between these SoC-based diagnostic instruments with other state-of-the-art diagnostics enables co-located multi-field turbulence fluctuation measurement.

scholarly journals Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Maher Assaad ◽  
Mohammed H. Alser
Keyword(s):  
Integrated Circuit ◽  
Reference Signal ◽  
Digital Processing ◽  
System On Chip ◽  
Frequency Multiplier ◽  
Experimental Results ◽  
Clock Signal ◽  
Phase Tracking ◽  
Frequency Locked Loops ◽  
On Chip

This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit. Moreover, it can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip (SoC). The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. The experimental results validate the expected phase tracking as well as the synthesizing properties. For the measurement and validation purpose, an input reference signal in the range of 1.94–2.62 MHz was injected; the generated clock signal has a higher frequency, and it is in the range of 124.2–167.9 MHz with a frequency step (i.e., resolution) of 0.168 MHz. The synthesized design requires 330 logic elements using the above Altera board.

scholarly journals A System-on-Chip Solution for a Low Power Active Capsule Endoscope with Therapeutic Capabilities for Clip Application in the Gastrointestinal Tract

2017 ◽  
Vol 02 (04) ◽  
pp. 1750005
Author(s):  
Oscar Alonso ◽  
Angel Diéguez ◽  
Sebastian Schostek ◽  
Marc O. Schurr
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
System On Chip ◽  
Capsule Endoscope ◽  
Implementation Challenges ◽  
Clip Application ◽  
Application Specific Integrated Circuit ◽  
On Chip ◽  
Wireless Capsule ◽  
Application Specific

This paper addresses the circuit implementation challenges resulting from the integration of a therapeutic clip in a magnetically maneuverable wireless capsule intended for colonoscopy. To deal with the size constraints typical of a capsule endoscope, an Application Specific Integrated Circuit (ASIC) has been designed specifically to habilitate the release of the therapeutic clip. The ASIC is a complete System on Chip (SoC) that incorporates a circuit for the low power release of the clip, thus overcoming the limitations of the power supply system. With a size of 14[Formula: see text]mm2, the ASIC can be incorporated in practically any capsule endoscope, consuming only an idle-state power of 1.5[Formula: see text]mW.

VLSI AND SYSTEM-ON-CHIP REDUNDANT COMPONENTS SYNTHESIS

2018 ◽  
pp. 33-39
Author(s):  
V. V. Rozanov ◽  
E. A. Suvorova
Keyword(s):  
Fault Tolerance ◽  
Integrated Circuit ◽  
System On Chip ◽  
Point Of View ◽  
Manufacturing Defects ◽  
Asic Design ◽  
Hardware Description ◽  
Early Design Stages ◽  
Chip Testing ◽  
On Chip

Redundancy - mostly used method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault tolerance. From Application Specified Integrated Circuit (ASIC) design point of view redundancy means area and power increasing. On early design stages, it is necessary to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation.

An On-Chip Clock Controller for Testing Fault in System on Chip

2013 ◽  
Vol 347-350 ◽  
pp. 724-728
Author(s):  
Wei Lin ◽  
Wen Long Shi
Keyword(s):  
Integrated Circuit ◽  
Test Pattern ◽  
Fault Coverage ◽  
System On Chip ◽  
Pattern Generation ◽  
Integrated Circuit Design ◽  
Scan Test ◽  
High Efficient ◽  
Transition Delay ◽  
On Chip

In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timing-related defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

System-on-chip upgrade of millimeter-wave imaging diagnostics for fusion plasma

2021 ◽  
Vol 92 (5) ◽  
pp. 053522
Author(s):  
Y. Zhu ◽  
J.-H. Yu ◽  
G. Yu ◽  
Y. Ye ◽  
Y. Chen ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
System On Chip ◽  
Fusion Plasma ◽  
Imaging Diagnostics ◽  
Millimeter Wave Imaging ◽  
Wave Imaging ◽  
On Chip

scholarly journals Millimeter-wave system-on-chip advancement for fusion plasma diagnostics

2018 ◽  
Vol 89 (10) ◽  
pp. 10H108 ◽  
Author(s):  
J.-H. Yu ◽  
Y.-T. Chang ◽  
K.-Y. Lin ◽  
C.-C. Chang ◽  
S.-F. Chang ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
Plasma Diagnostics ◽  
System On Chip ◽  
Wave System ◽  
Fusion Plasma ◽  
On Chip

Feasibility of the Microcomputers for the ADDASAT Capsule

2016 ◽  
Vol 841 ◽  
pp. 309-314
Author(s):  
Dragos Ronald Rugescu
Keyword(s):  
Integrated Circuit ◽  
System On Chip ◽  
Circuit Asic ◽  
Rf Communication ◽  
Size Constraints ◽  
Extreme Degree ◽  
The Future ◽  
Application Specific Integrated Circuit ◽  
On Chip ◽  
Application Specific

One of the most challenging problems in developing the astrionics of the recoverable orbital ADDAHORSE microcapsule is represented by the power and size constraints which require an extreme degree of miniaturization. The size, mass and power requirements of the electronic and computing (astrionics) on-board control and command equipment can be conveniently reduced by designing an Application Specific Integrated Circuit (ASIC) which integrates sensors, autopilot logic, drivers, RF communication and interface subsystems in a single, combined SoC (System-on-Chip). The feasibility of such a device is discussed here within the bounds of the ADDAHORSE project which was proposed for structural funding in Romania in 2014. This study was conducted by the Center for Innovation and Development in the Exploration of Space (CIDES) in the emerging Făgăraș facility of the future Făgăraș Space Center in Romania.

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