Multislice imaging of integrated circuits by precession X-ray ptychography

2018 ◽  
Vol 74 (1) ◽  
pp. 66-70 ◽  
Author(s):  
Kei Shimomura ◽  
Makoto Hirose ◽  
Yukio Takahashi
Keyword(s):  
Integrated Circuits ◽  
Sample Preparation ◽  
Present Method ◽  
Three Dimensional ◽  
Data Sets ◽  
X Ray ◽  
Phase Images ◽  
Tilt Series ◽  
Silicon Vias ◽  
Multislice Imaging

A method for nondestructively visualizing multisection nanostructures of integrated circuits by X-ray ptychography with a multislice approach is proposed. In this study, tilt-series ptychographic diffraction data sets of a two-layered circuit with a ∼1.4 µm gap at nine incident angles are collected in a wideQrange and then artifact-reduced phase images of each layer are successfully reconstructed at ∼10 nm resolution. The present method has great potential for the three-dimensional observation of flat specimens with thickness on the order of 100 µm, such as three-dimensional stacked integrated circuits based on through-silicon vias, without laborious sample preparation.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Three Dimensional X-Ray Computed Tomography in Materials Science

MRS Bulletin ◽  
1988 ◽  
Vol 13 (1) ◽  
pp. 13-18 ◽  
Author(s):  
J.H. Kinney ◽  
Q.C. Johnson ◽  
U. Bonse ◽  
M.C. Nichols ◽  
R.A. Saroyan ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
High Resolution ◽  
Sample Preparation ◽  
Visible Light ◽  
Three Dimensional ◽  
Materials Characterization ◽  
Imaging Technology ◽  
X Ray ◽  
X Ray Imaging ◽  
Visible Light Imaging

Imaging is the cornerstone of materials characterization. Until the middle of the present century, visible light imaging provided much of the information about materials. Though visible light imaging still plays an extremely important role in characterization, relatively low spatial resolution and lack of chemical sensitivity and specificity limit its usefulness.The discovery of x-rays and electrons led to a major advance in imaging technology. X-ray diffraction and electron microscopy allowed us to characterize the atomic structure of materials. Many materials vital to our high technology economy and defense owe their existence to the understanding of materials structure brought about with these high-resolution methods.Electron microscopy is an essential tool for materials characterization. Unfortunately, electron imaging is always destructive due to the sample preparation that must be done prior to imaging. Furthermore, electron microscopy only provides information about the surface of a sample. Three dimensional information, of great interest in characterizing many new materials, can be obtained only by time consuming sectioning of an object.The development of intense synchrotron light sources in addition to the improvements in solid state imaging technology is revolutionizing materials characterization. High resolution x-ray imaging is a potentially valuable tool for materials characterization. The large depth of x-ray penetration, as well as the sensitivity of absorption crosssections to atomic chemistry, allows x-ray imaging to characterize the chemistry of internal structures in macroscopic objects with little sample preparation. X-ray imaging complements other imaging modalities, such as electron microscopy, in that it can be performed nondestructively on metals and insulators alike.

scholarly journals Determination of crystallographic intensities from sparse data

IUCrJ ◽  
2015 ◽  
Vol 2 (1) ◽  
pp. 29-34 ◽  
Author(s):  
Kartik Ayyer ◽  
Hugh T. Philipp ◽  
Mark W. Tate ◽  
Jennifer L. Wierman ◽  
Veit Elser ◽  
...  
Keyword(s):  
Diffraction Data ◽  
Crystal Size ◽  
Three Dimensional ◽  
Sparse Data ◽  
Data Sets ◽  
X Rays ◽  
Diffraction Intensity ◽  
X Ray ◽  
Proof Of Principle

X-ray serial microcrystallography involves the collection and merging of frames of diffraction data from randomly oriented protein microcrystals. The number of diffracted X-rays in each frame is limited by radiation damage, and this number decreases with crystal size. The data in the frame are said to be sparse if too few X-rays are collected to determine the orientation of the microcrystal. It is commonly assumed that sparse crystal diffraction frames cannot be merged, thereby setting a lower limit to the size of microcrystals that may be merged with a given source fluence. TheEMCalgorithm [Loh & Elser (2009),Phys. Rev. E,80, 026705] has previously been applied to reconstruct structures from sparse noncrystalline data of objects with unknown orientations [Philippet al.(2012),Opt. Express,20, 13129–13137; Ayyeret al.(2014),Opt. Express,22, 2403–2413]. Here, it is shown that sparse data which cannot be oriented on a per-frame basis can be used effectively as crystallographic data. As a proof-of-principle, reconstruction of the three-dimensional diffraction intensity using sparse data frames from a 1.35 kDa molecule crystal is demonstrated. The results suggest that serial microcrystallography is, in principle, not limited by the fluence of the X-ray source, and collection of complete data sets should be feasible at, for instance, storage-ring X-ray sources.

Silicon Interposer Featuring Novel Electrical and Optical TSVs

2012 ◽  
Author(s):  
Paragkumar A. Thadesar ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Heat Sink ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
System Level ◽  
Performance Improvements ◽  
Fine Pitch ◽  
3D Integrated Circuits ◽  
Photonic Interconnects ◽  
Silicon Vias

Three-dimensional (3D) integrated circuits (ICs) yield system level performance improvements by providing high-bandwidth communication as well as opportunity for heterogeneous integration. It is envisioned that an area array of 3D stacked ICs can be interconnected using dense fine-pitch electrical and photonic interconnects on a silicon interposer. This paper presents a mechanically robust “thick” silicon interposer with novel electrical through-silicon vias (TSVs) and optical TSVs. The novel electrical TSVs described include polymer-clad TSVs and polymer-embedded vias. An advantage of using thick silicon interposer is that microchannels can be integrated in the thick silicon interposer to transfer a coolant to the 3D ICs with interlayer microfluidic heat sink or for the direct integration of a microfluidic heat-sink in the silicon interposer. However, as the thickness of silicon interposer increases, TSV electrical parasitics increase. Moreover, the coefficient of thermal expansion (CTE) mismatch between the copper TSV and silicon causes reliability issues. To reduce TSV capacitance as well as to reduce TSV stresses, polymer-clad electrical TSVs were fabricated. Using the same photodefinable polymer used for the cladding of electrical TSVs, optical TSVs were fabricated and characterized.

scholarly journals System-on-chip testing

2019 ◽  
Author(s):  
Παναγιώτης Γεωργίου
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Rectangle Packing ◽  
3D Ics ◽  
Systems On Chip ◽  
Self Test ◽  
Chip Testing ◽  
On Chip ◽  
Silicon Vias ◽  
Access Mechanisms

Διανύουμε ήδη την εποχή του "Ίντερνετ των Πραγμάτων". Οι κοινές συσκευές που χρησιμοποιούμε καθημερινά, συνδέονται μεταξύ τους και γίνονται "εξυπνότερες" με ραγδαίους ρυθμούς. Σε κάθε τέτοια συσκευή βρίσκεται ένα Σύστημα σε Ολοκληρωμένο (Systems-On-Chip ή SoC). Το SoC εξελίσσεται συνεχώς, για να ικανοποιηθούν οι συνεχώς αυξανόμενες απαιτήσεις της νέας εποχής. Τα τρι-διάστατα ολοκληρωμένα κυκλώματα (three-dimensional integrated circuits - 3D-ICs) είναι μια υποσχόμενη λύση για να ικανοποιήσουν τις απαιτήσεις τις νέας εποχής και φαίνεται να εξασφαλίζουν τη συνέχιση του Νόμου του Moore στο άμεσο μέλλον. Τα 3D-ICs πετυχαίνουν υψηλότερη πυκνότητα πυλών και καλύτερη απόδοση από τα συμβατικά SoC και μειώνουν το κόστος διασύνδεσης και κατανάλωσης. Πρόσφατα, οι κατασκευαστικές εταιρείες ολοκληρωμένων συστημάτων κυκλοφόρησαν προϊόντα βασισμένα σε 3D-ICs. Η έρευνα αυτή εστιάζει στην ανάπτυξη νέων αρχιτεκτονικών μηχανισμού πρόσβασης ελέγχου (Test Access Mechanisms - TAMs) και νέων μεθόδων χρονοπρογραμματισμού ελέγχου ορθής λειτουργίας για 3D-SoCs, οι οποίες εκμεταλλεύονται την υψηλή ταχύτητα που προσφέρουν οι ειδικές κάθετες διασυνδέσεις μέσω-πυριτίου (Through Silicon Vias - TSVs), ενώ η κατανάλωση ισχύος και η θερμότητα πρέπει να διατηρηθούν κάτω από ορισμένα επίπεδα. Εισάγουμε μία νέα αρχιτεκτονική TAM για 3D SoCs, η οποία ελαχιστοποιεί το χρόνο ελέγχου ορθής λειτουργίας, το πλήθος των TSVs και τις γραμμές της αρχιτεκτονικής TAM που χρησιμοποιούνται για να μεταφερθούν τα δεδομένα ελέγχου. Ο χρονοπρογραμματισμός του ελέγχου ορθής λειτουργίας υπολογίζεται από μία αποδοτική μέθοδο χρονικής πολυπλεξίας και μία πολύ αποδοτική μέθοδο βελτιστοποίησης που βασίζεται στους αλγορίθμους rectangle-packing και simulated-annealing. Πειραματικά αποτελέσματα δείχνουν έως και 9.6 φορές εξοικονόμηση στο χρόνο ελέγχου με την προτεινόμενη μέθοδο, ειδικά κάτω από αυστηρά όρια για την κατανάλωση ισχύος και τη θερμότητα. Η προηγούμενη μέθοδος είναι συμβατή μόνο με TAMs που βασίζονται σε αρτηρίες (buses), οι οποίες απαιτούν διασυνδέσεις μεγάλου μήκους και πολλά buffers σε κάθε επίπεδο του 3D-IC, επομένως δεν καταφέρνουν να εκμεταλλευτούν πλήρως τις υψηλές συχνότητες των TSVs. Προτείνουμε μία νέα αρχιτεκτονική TAM βασισμένη στη χρονική πολυπλεξία, που χρησιμοποιεί σειριακές αλυσίδες (daisy-chains) για να ξεπεράσουμε τους περιορισμούς της προηγούμενης μεθόδου. Η μέθοδος αυτή προσφέρει μεγαλύτερα κέρδη όσον αφορά το χρόνο ελέγχου ορθής λειτουργίας και το κόστος διασύνδεσης. Η έρευνα αυτή εστιάζει στη βελτίωση ανίχνευσης σφαλμάτων συσκευών βασιζόμενων σε επεξεργαστή. Οι ολοένα αυξανόμενες απαιτήσεις της αγοράς για υψηλότερη υπολογιστική απόδοση σε μικρότερο κόστος και χαμηλότερη κατανάλωση ισχύος, οδηγεί τους κατασκευαστές στην ανάπτυξη νέων μικροεπεξεργαστών, που εισάγουν νέες προκλήσεις στον έλεγχο συσκευών βασιζόμενων σε επεξεργαστή. Η ανάγκη ελέγχου των συσκευών αυτών κατά τη διάρκεια της κανονικής τους λειτουργίας, επιβάλλουν τη συμπληρωματική χρήση μεθόδων ελέγχου που δεν επηρεάζουν τη λειτουργία, όπως ο «αυτοέλεγχος βασισμένος σε λογισμικό» (Software-Based Self-Test - SBST). Οι περισσότερες τεχνικές SBST στοχεύουν μόνο το μοντέλο σφαλμάτων stuck-at, που δεν αρκεί για την ανίχνευση πολλών σφαλμάτων. Επίσης, οι τεχνικές SBST απαιτούν εκτενή ανθρώπινη ενασχόληση με μεγάλους χρόνους ανάπτυξης των προγραμμάτων ελέγχου. Επιπλέον, περιλαμβάνουν την κοστοβόρα, από άποψη υπολογιστική ισχύος, εξομοίωση σφαλμάτων SoCs με εκατομμύρια πύλες για εκατομμύρια κύκλους ρολογιού, χρησιμοποιώντας πολλαπλά μοντέλα σφαλμάτων και εξειδικευμένους λειτουργικούς εξομοιωτές. Εισάγουμε την πρώτη μέθοδο που δεν μεροληπτεί υπέρ κάποιου συγκεκριμένου μοντέλου σφαλμάτων. Η μέθοδος αυτή προσφέρει σύντομο χρόνο δημιουργίας προγραμμάτων ελέγχου, υπό αυστηρό περιορισμό στο χρόνο ελέγχου ορθής λειτουργίας και στο μέγεθος των προγραμμάτων ελέγχου. Τα προγράμματα ελέγχου αξιολογούνται από μία νέα αποδοτική πιθανοτική μέθοδο SBST, εκμεταλλευόμενη την αρχιτεκτονική του επεξεργαστή, καθώς και τη netlist του επεξεργαστή σε επίπεδο πυλών που έχει προκύψει από σύνθεση. Η προτεινόμενη μετρική που βασίζεται στα output deviations είναι πολύ γρήγορη καθώς δεν απαιτεί τη χρονοβόρα διαδικασία της εξομοίωσης σφαλμάτων και μπορεί να εφαρμοστεί σε οποιαδήποτε μέθοδο που βασίζεται στην τεχνική SBST.

A new algorithm for the reconstruction of protein molecular envelopes from X-ray solution scattering data

2019 ◽  
Vol 52 (5) ◽  
pp. 937-944
Author(s):  
John Badger
Keyword(s):  
Protein Structures ◽  
Three Dimensional ◽  
Protein Molecule ◽  
Scattering Data ◽  
Data Sets ◽  
Low Resolution ◽  
Jones Potential ◽  
X Ray ◽  
Pair Distance Distribution Function ◽  
Protein Shape

At sufficiently low resolution, the scattering density within the volume occupied by a well folded protein molecule appears relatively flat. By enforcing this condition, three-dimensional protein molecular envelopes may be reconstructed using information obtained from X-ray solution scattering profiles. A practical approach for solving the low-resolution structures of protein molecules from solution scattering data involves modelling the protein shape using a set of volume-filling points (`beads') and transforming the scattering data to a more convenient target, the pair distance distribution function, P(r). Using algorithms described here, the beads interact via a modified Lennard–Jones potential and their positions are adjusted and confined until they fit the expected protein volume and agreement with P(r) is obtained. This methodology allows the protein volume to be modelled by an arbitrary, user-defined number of beads, enabling the rapid reconstruction of protein structures of widely varying sizes. Tests carried out with a variety of synthetic and experimental data sets show that this approach gives efficient and reliable determinations of protein molecular envelopes.

A Study of Defects Due to Surface Processing in Silicon by Means of X-Ray Extinction Contrast Topography

1964 ◽  
Vol 8 ◽  
pp. 48-58 ◽  
Author(s):  
E. S. Meieran ◽  
K. E. Lemons
Keyword(s):  
Sample Preparation ◽  
Surface Treatment ◽  
Three Dimensional ◽  
Routine Laboratory ◽  
Surface Processing ◽  
X Ray ◽  
Processing Step ◽  
Processing Variables ◽  
Laboratory Procedures ◽  
Dimensional Picture

AbstractIn order to study the effects of processing variables on the defect contents of silicon wafers, an X-ray extinction contrast camera was designed and constructed to fit on the standard GE XRD-5 table. The camera, in its normal operating position, can be routinely used without interfering with the emission or diffraction instrumentation of the unit, and also can be mounted on the diffractometer stage for diffraction line breadth analysis. Routine laboratory procedures including sample preparation and mounting, film types, and film exposure and development are outlined.The correlation between extinction contrast topographs and optical photographs of sawed wafers is presented. Wafers were examined in the sawed, lapped, and chemically polished conditions. Subsequent to each processing step in the surface treatment of wafers, a series of topographs was made using four different crystal orientations. In this manner the three-dimensional picture of the defects is obtained, as are the Burger's vectors of all dislocations. It appears that internal defects such as dislocations are more uniformly distributed in lapped and chemically polished wafers than in sawed and chemically polished wafers. Furthermore, different doping impurities and levels cause different amounts of contrast in the dislocation images.

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