Optical alignment and compensation control of die bonder for chips containing through-silicon vias

2019 ◽  
Vol 40 (6) ◽  
pp. 917-923
Author(s):  
Chern Sheng Lin ◽  
Chang-Yu Hung ◽  
Chung Ting Chen ◽  
Ke-Chun Lin ◽  
Kuo Liang Huang
Keyword(s):  
Integrated Circuit ◽  
Dynamic Imaging ◽  
Test Time ◽  
Reference Image ◽  
Through Silicon Vias ◽  
Content Type ◽  
Compensation Control ◽  
Compact Size ◽  
Optical Alignment ◽  
Silicon Vias

Purpose This study aims to present an optical alignment and compensation control of die bonder for chips containing through-silicon vias and develop three-dimensional integrated circuit stacked packaging for compact size and multifunction. Design/methodology/approach The machine vision, optical alignment method and sub-pixel technology in dynamic imaging condition are used. Through a comparison of reference image, the chip alignment calibration can improve machine accuracy and stability. Findings According to the experimental data and preliminary results of the analysis, accuracy can be achieved within the desired range, and the accuracy is much better than traditional die bonder equipment. The results help further research in die bonder for chips containing through-silicon vias. Originality/value In subsequent testing of the chip, the machine can simultaneously test multiple chips to save test time and increase productivity.

scholarly journals Improvement on Fully Filled Through Silicon Vias by Optimized Sputtering and Electroplating Conditions

Materials ◽  
2019 ◽  
Vol 12 (22) ◽  
pp. 3713 ◽  
Author(s):  
Fei Zhao
Keyword(s):  
Electron Microscope ◽  
Integrated Circuit ◽  
Seed Layer ◽  
High Reliability ◽  
Through Silicon Vias ◽  
X Ray ◽  
Layer Structures ◽  
Silicon Vias ◽  
Scanning Electron

The high reliability of electroplating through silicon vias (TSVs) is an attractive hotspot in the application of high-density integrated circuit packaging. In this paper, improvements for fully filled TSVs by optimizing sputtering and electroplating conditions were introduced. Particular attention was paid to the samples with different seed layer structures. These samples were fabricated by different sputtering and treatment approaches, and accompanied with various electroplating profile adjustments. The images were observed and characterized by X-ray equipment and a scanning electron microscope (SEM). The results show that optimized sputtering and electroplating conditions can help improve the quality of TSVs, which could be interpreted as the interface effect of the TSV structure.

A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang
Keyword(s):  
Integrated Circuit ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Micro Channel ◽  
3D Ic ◽  
Through Silicon Vias ◽  
3D Ics ◽  
Three Dimensional Integrated Circuit ◽  
Silicon Vias ◽  
Cooling Model

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

scholarly journals Thermal management of the through silicon vias in 3-D integrated circuits

2019 ◽  
Vol 23 (4) ◽  
pp. 2157-2162
Author(s):  
Kang-Jia Wang ◽  
Chu-Xia Hua ◽  
Hong-Chang Sun
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Design Guidelines ◽  
Thermal Design ◽  
Through Silicon Via ◽  
Through Silicon Vias ◽  
Factors Affecting ◽  
Two Factors ◽  
Circuit Integration ◽  
Silicon Vias

The through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit integration. However, its size and the property of the filled-materials are two factors affecting the thermal behavior of the integrated circuits. In this paper, we design 3-D integrated circuits with different through silicon via models and analyze the effect of different material-filled through silicon vias, aspect ratio and thermal conductivity of the dielectric on the steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for through silicon vias in 3-D integrated circuits.

A Path Toward Non-Destructive 3D Metrology for Through-Silicon Vias

2011 ◽  
Vol 2011 (1) ◽  
pp. 000017-000024 ◽  
Author(s):  
Jeff Gelb ◽  
LayWai Kong ◽  
Luke Hunter ◽  
Allen Gu ◽  
Tiffany Fong ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Through Silicon Vias ◽  
Modern Approach ◽  
Critical Dimensions ◽  
X Ray ◽  
Imaging Geometry ◽  
3D Stacking ◽  
Silicon Vias ◽  
3D Metrology ◽  
Non Destructive

As integrated circuit designs are pushed to tighter dimensions, chip real-estate is becoming of increasing value. Much like the growth of a developing city, a common modern approach is to grow the circuits upwards, building one layer on top of another. In this 3D stacking approach, the common issue lies in how to connect the multiple layers, for which direct connections through the silicon substrates have been found to produce the smallest footprint. These through-silicon vias (TSVs) are currently the subject of heavy research and development (R&D) investigation and their efficiencies are, in part, directly related to the occurrence or absence of voids within the metal structures. 3D x-ray microscopy (XRM) has recently been pushed to unprecedented resolution levels and may fit the inspection needs of the TSV R&D community. Using a unique projection-based micro-CT imaging geometry, entire packages may be inspected with as high as 1 μm resolution. This technique delivers non-destructive metrology of the metal fills as well as the post-etch regions in 3D, without the need for physical cutting or sectioning. By employing x-ray optics, resolution as high as 50 nm is now routinely achievable, allowing the detection of far sub-micron voids within the post-metallization TSV structures. These results may be further analyzed for void sizes and void volume fractions per via. Post-etch samples are also well-visualized using this technique, which allows high-resolution inspection of the side walls as well as measurement of the critical dimensions using the same system as for the post-metallization structures.

scholarly journals Thermal management of the hotspots in 3-D integrated circuits

2018 ◽  
Vol 22 (4) ◽  
pp. 1685-1690 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Cui-Ling Li ◽  
Guo-Dong Wang ◽  
Hong-Wei Zhu
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Vertical Integration ◽  
Integrated Circuit ◽  
Design Guidelines ◽  
Thermal Design ◽  
Micro Channel ◽  
Through Silicon Vias ◽  
Microchannel Cooling ◽  
Silicon Vias

Vertical integration for microelectronics possesses significant challenges due to its fast dissipation of heat generated in multiple device planes. This paper focuses on thermal management of a 3-D integrated circuit, and micro-channel cooling is adopted to deal with the 3-D integrated circuitthermal problems. In addition, thermal through-silicon vias are also used to improve the capacity of heat trans-mission. It is found that combination of microchannel cooling and thermal through-silicon vias can remarkably alleviate the hotspots. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3-D integrated circuits.

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