On the methodology of calculating volume charge density in a MIFGMOS substrate using Poisson’s equation

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Francisco Javier Plascencia Jauregui ◽  
Agustín Santiago Medina Vazquez ◽  
Edwin Christian Becerra Alvarez ◽  
José Manuel Arce Zavala ◽  
Sandra Fabiola Flores Ruiz
Keyword(s):  
Metal Oxide ◽  
Charge Density ◽  
Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Poisson’S Equation ◽  
Oxide Semiconductor ◽  
Volume Charge ◽  
Poisson's Equation ◽  
Content Type ◽  
Volume Charge Density

Purpose This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor. Design/methodology/approach Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths. Findings The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena. Originality/value The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.

Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric

2009 ◽  
Vol 95 (3) ◽  
pp. 033118 ◽  
Author(s):  
Yanli Pei ◽  
Chengkuan Yin ◽  
Toshiya Kojima ◽  
Masahiko Nishijima ◽  
Takafumi Fukushima ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
High Density ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Memory Characteristics ◽  
Metal Oxide Semiconductor Capacitor

Memory Operation of Silicon Quantum-Dot Floating-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

2001 ◽  
Vol 40 (Part 2, No. 7B) ◽  
pp. L721-L723 ◽  
Author(s):  
Atsushi Kohno ◽  
Hideki Murakami ◽  
Mitsuhisa Ikeda ◽  
Seiichi Miyazaki ◽  
Masataka Hirose
Keyword(s):  
Quantum Dot ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Silicon Quantum Dot

Light-Induced Carrier Transfer in NiSi-Nanodots/Si-Quantum-Dots Hybrid Floating Gate in Metal–Oxide–Semiconductor Structures

2010 ◽  
Vol 49 (4) ◽  
pp. 04DJ04 ◽  
Author(s):  
Naoya Morisawa ◽  
Mitsuhisa Ikeda ◽  
Sho Nakanishi ◽  
Akira Kawanami ◽  
Katsunori Makihara ◽  
...  
Keyword(s):  
Quantum Dots ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Carrier Transfer ◽  
Semiconductor Structures ◽  
Si Quantum Dots

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Abhay Sanjay Vidhyadharan ◽  
Sanjay Vidhyadharan
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Low Voltage ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Schmitt Trigger ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Requirement ◽  
Content Type

Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Alok Kumar Mishra ◽  
Vaithiyanathan D. ◽  
Yogesh Pal ◽  
Baljit Kaur
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Power Saving ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Read Operation ◽  
Data Line ◽  
Sram Cell ◽  
Pmos Transistor

Purpose This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell. Design/methodology/approach The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate. Findings Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively. Originality/value The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

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