10-bit High-speed CMOS comparator with offset cancellation technique

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

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High-speed CMOS track-and-hold with an offset cancellation replica circuit

Proceedings of 2010 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2010.5537545 ◽

2010 ◽

Cited By ~ 1

Author(s):

Mahzad Azarmehr ◽

Rashid Rashidzadeh ◽

Majid Ahmadi

Keyword(s):

High Speed ◽

Offset Cancellation

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Sense amplifier offset cancellation and replica timing calibration for high-speed SRAMs

2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS) ◽

10.1109/lascas.2018.8399941 ◽

2018 ◽

Cited By ~ 1

Author(s):

Roman Fragasse ◽

Brian Dupaix ◽

Ramy Tantawy ◽

Todd James ◽

Waleed Khalil

Keyword(s):

High Speed ◽

Offset Cancellation ◽

Sense Amplifier

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A New Differential-amplifier-based Offset-Cancellation Sense Amplifier (DOCSA) for High-speed SRAMs in Scaled-down CMOS Technology

10.7567/ssdm.2009.i-5-3l ◽

2009 ◽

Author(s):

H. Ikeda ◽

K. Takeda ◽

M. Nomura ◽

Y. Hayashi

Keyword(s):

High Speed ◽

Cmos Technology ◽

Differential Amplifier ◽

Offset Cancellation ◽

Sense Amplifier

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An ultra high-speed high-resolution low-offset low-power voltage comparator with a reliable offset cancellation method for high-performance applications in 0.18 µm CMOS technology

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-015-0604-1 ◽

2015 ◽

Vol 85 (1) ◽

pp. 181-192 ◽

Cited By ~ 7

Author(s):

Ali Baradaranrezaeii ◽

Obalit Shino ◽

Khayrollah Hadidi ◽

Abdollah Khoei

Keyword(s):

High Resolution ◽

Low Power ◽

High Speed ◽

High Performance ◽

Cmos Technology ◽

Voltage Comparator ◽

Offset Cancellation ◽

Ultra High Speed ◽

Low Offset

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A high-speed low-power CMOS comparator using auto-zero offset cancellation technique

Proceedings of the 24th symposium on Integrated circuits and systems design - SBCCI '11 ◽

10.1145/2020876.2020885 ◽

2011 ◽

Cited By ~ 1

Author(s):

Sandro A.P. Haddad ◽

Ivan Nascimento

Keyword(s):

Low Power ◽

High Speed ◽

Offset Cancellation ◽

Low Power Cmos ◽

Zero Offset

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A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC

Journal of Circuits System and Computers ◽

10.1142/s0218126613500618 ◽

2013 ◽

Vol 22 (07) ◽

pp. 1350061 ◽

Cited By ~ 2

Author(s):

ZHANGMING ZHU ◽

WEITIE WANG ◽

YUHENG GUAN ◽

SHUBIN LIU ◽

YU XIAO ◽

...

Keyword(s):

Monte Carlo Simulation ◽

Monte Carlo ◽

Low Power ◽

High Speed ◽

Cmos Process ◽

Amplifier Circuit ◽

Offset Cancellation ◽

Offset Voltage ◽

Low Offset

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

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