A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC
2013 ◽
Vol 22
(04)
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pp. 1350018
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Keyword(s):
A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.
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2013 ◽
Vol 22
(07)
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pp. 1350061
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2019 ◽
Vol 9
(1S5)
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pp. 41-44
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2014 ◽
Vol 598
◽
pp. 365-370
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2019 ◽
Vol 8
(4)
◽
pp. 4053-4057
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2013 ◽
Vol 321-324
◽
pp. 367-371
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2014 ◽
Vol 23
(05)
◽
pp. 1450059
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