scholarly journals Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 445
Author(s):  
Hou ◽  
Du ◽  
Yang ◽  
Liu ◽  
Liu
Keyword(s):  
Electrostatic Discharge ◽  
Cmos Process ◽  
Silicon Area ◽  
Lateral Dimension ◽  
Esd Protection ◽  
Layout Area ◽  
Protection Capability ◽  
P Type ◽  
Area Efficient

The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.

scholarly journals Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

2020 ◽  
Vol 15 (1) ◽  
Author(s):  
Ruibo Chen ◽  
Hongxia Liu ◽  
Wenqiang Song ◽  
Feibo Du ◽  
Hao Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Triggering Mechanism ◽  
Esd Protection ◽  
Tcad Simulation ◽  
P Type ◽  
28 Nm ◽  
Latch Up

Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

scholarly journals Analysis of Non-Uniform Current Distribution in Multi-Fingered and Low-Voltage-Triggered LVTSCR

2021 ◽  
Vol 27 (1) ◽  
pp. 41-47
Author(s):  
Zijie Zhou ◽  
Xiangliang Jin ◽  
Yang Wang ◽  
Peng Dong ◽  
Yan Peng ◽  
...  
Keyword(s):  
Low Voltage ◽  
Electrostatic Discharge ◽  
Coupling Effect ◽  
Oxide Semiconductor ◽  
The Novel ◽  
Type Region ◽  
Uniform Current ◽  
Heavily Doped ◽  
Layout Area ◽  
P Type

Laterally Diffused Metal Oxide Semiconductor Silicon-Controlled Rectifier (LDMOS-SCR) is usually used in Electrostatic Discharge (ESD) protection. LDMOS-SCR discharges current by parasitic SCR, but the MOS in it cannot work when parasitic SCR is stabilized. To further enhance the Electrostatic Discharge (ESD) discharging capability of LDMOS-SCR, a novel high failure current LDMOS-SCR with 12 V operation voltage is fabricated and verified in a 0.18-um high-voltage Bipolar-CMOS-DMOS (BCD) process. Compared with conventional LDMOS-SCR, the novel LDMOS-SCR (LDMOS-SCR-R) introduced a heavily doped p-type region, which is located between the heavily doped n-type and p-type regions of Cathode and is connected with the gate. The adding p-well resistance can drop the voltage on the gate, and the gate with p-well resistance also has resistance and capacitance coupling effect. According to the results of the transmission line pulse test (TLP), the voltage applied to the gate by increasing the p-well resistance plays a major role in the device working mechanism. Under the same device size, LDMOS-SCR-R has higher It2 (8.6 A) than conventional LDMOS (2.21 A) or LDMOS-SCR (6.62 A) in TLP results. Compared with LDMOS-SCR, the failure current of LDMOS-SCR-R increases by 30 %, and the FOM of LDMOS-SCR-R increases by 34 %. The response of LDMOS-SCR-R is also faster than that of LDMOS-SCR under larger current conditions. In addition, the phenomenon in TLP results is consistent with simulation results. The proposed LDMOS-SCR-R can effectively increase failure current without affecting the device’s design window, and the additional p-type region will not increase the layout area.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

2007 ◽  
Author(s):  
Yuan-Wen Hsiao ◽  
Ming-Dou Ker ◽  
Po-Yen Chiu ◽  
Chun Huang ◽  
Yuh-Kuang Tseng
Keyword(s):  
High Speed ◽  
Cmos Process ◽  
Esd Protection
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