Advanced Multifunctional Temporary Bonding Materials with Heterogeneous Integrated Properties for Various Advanced Packaging Applications

2019 ◽  
Author(s):  
Xiao Liu ◽  
Dongshun Bai ◽  
Lisa Kirchner ◽  
Rama Puligadda ◽  
Tony Flaim
Keyword(s):  
Temporary Bonding ◽  
Advanced Packaging

Wafer Thinning for Advanced Packaging Applications

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-26
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Scott Kroeger
Keyword(s):  
Low Cost ◽  
High Volume ◽  
Alternative Methods ◽  
Critical Element ◽  
Wafer Level ◽  
Temporary Bonding ◽  
Scale Down ◽  
Advanced Packaging ◽  
Wafer Thinning ◽  
Etch Profile

Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. The high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry. Lower-cost advanced packaging concepts have been developed and are now in high-volume production. Recently, alternative methods for exploiting the z-direction have turned to variations of Fan-Out Wafer Level Packaging (FOWLP), which do not include TSVs. In many of these concepts there is a need to thin the wafer to remove all of the silicon while being selective and not etching a variety of other films that include oxides, nitrides, and metals. In addition, there can be temporary bonding adhesives and mold compounds encapsulating the chips; these must remain undamaged. Another critical element of a successful process is the ability to control the profile of the silicon etch to provide uniform removal. The single wafer wet etching techniques and advanced process control developed for TSV Reveal are applicable to these structures and provide a low-cost alternative to CMP and Plasma processes. To successfully execute the process, several characteristics must be met: the silicon overburden depth and profile need to be determined, the overburden thinning etch needs a fast sculpting etchant, and the finishing etchant needs to be selective to materials that will be exposed at the completion of the etch. In addition, the tool used to perform this sequence needs to have the correct metrology capability, along with properly chosen etchants. Similarly, it is not sufficient to know the required etch profile, the software must be able to execute a unique etch profile for each wafer. In this fashion, the finishing etch time can be kept to a minimum. This is important, as many of the selective etchants have a slow etch rate, and adhesives used do not always hold up to exposure to the chemistries involved for long periods. This paper discusses the use of wet etch wafer thinning processes for new FOWLP applications.

Laser Debonding for 2.5D, 3D and Emerging Advanced Packaging Solutions

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-21
Author(s):  
T. Uhrmann ◽  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Martin Eibelhuber ◽  
Harald Wiesbauer ◽  
...  
Keyword(s):  
High Temperature ◽  
Temperature Stability ◽  
Critical Parameters ◽  
Process Window ◽  
Uv Laser ◽  
High Temperature Stability ◽  
Process Technology ◽  
Temporary Bonding ◽  
Advanced Packaging ◽  
Adhesive Materials

In recent years temporary bonding has evolved to a widely used process technology as it is an enabling process for many products relyinnovel solutions are typically assessed on two key criteria which are a broad process window and cost effectiveness. Thus in this paper these criteria will be discussed in more detail for the case of UV laser debonding with respect to wafer level packaging. By temporary bonding the thin or to be thinned device wafer is bonded to a carrier wafer by an adhesive interlayer to provide sufficient mechanical support which is crucial for many downstream processes. In the past several different technologies have been studied and implemented. A major differentiation factor between the offered solutions is the debonding method, including separation processes at room or elevated temperatures. Nowadays a particular focus is on UV laser debonding as it offers several advantages, as the debonding process can be performed at room temperature with fast process times and force free separation. Furthermore crosslinking adhesive materials with high temperature stability can be used. This can be achieved due to the high intensity UV light provided by an excimer laser system which is absorbed by the polymer close to the carrier surface and breaks the chemical bonds. The low debonding temperature in combination with high temperature stability of the adhesives leads to a broad process window for the temporary bonded stack. In addition transparent adhesive materials can be used in combination with the glass carrier to support better visibility of alignment marks within the bond interface. However, for industrial requirement besides the technical advantages the most critical parameters are ease of implementation, throughput and costs. In this paper we will review integration principles for advanced packaging as well as new devices that utilize temporary bonding. Special focus will also be put on upcoming demands for future device concepts. A short discussion will discuss temporary bonding methods and materials, benefits and drawbacks of each one. In the following laser debonding will be discussed as a focus topic for next generation packaging process technology. Laser debonding is already being applied in volume for couple of technologies, focussing on different wavelengths. We will focus on a newly developed technology, using UV solid state laser technology. Here, we will discuss all relevant process parameter, critical process steps along with reliability of different laser debonding material systems.

Challenges of Scalable 2.5D IC Assembly

2015 ◽  
Vol 12 (3) ◽  
pp. 123-128
Author(s):  
Liang Wang ◽  
Charles G. Woychik ◽  
Guilian Gao ◽  
Grant Villavicencio ◽  
Scott McGrath ◽  
...  
Keyword(s):  
High Volume ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
High Yield ◽  
Design Stage ◽  
Advantages And Disadvantages ◽  
Interconnect Delay ◽  
Temporary Bonding ◽  
Thermocompression Bonding ◽  
Advanced Packaging

Driven by key metrics, including higher computing performance, lower power consumption, smaller form factor, increased bandwidth, and reduced latency (interconnect delay), the semiconductor interconnect technology is transitioning to 2.5D and gaining acceptance in the industry, as an increasing number of products are beginning to enter volume manufacturing. To transition from today's low volumes to high volume manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput), and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process, and integration choices. With these concerns as a backdrop, our article will discuss our approach to optimizing 2.5D assembly for HVM. This article starts with a review of our test vehicle and our overall choices of substrate, interposer, and die dimensions. Three different 2.5D assembly approaches that have been investigated for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. It is our finding that for achieving high yield and reliability, in the design stage of the system detailed considerations must be given to not only the electrical performance and signal integrity but also the thermal and mechanical behavior of the system in operation as well as the entire process history. This article reports our results from critical areas including temporary bonding, thermocompression bonding, mass reflow, thin wafer/die handling, flux, underfill, and molding. This article also presents our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In the last portion of this article, recommendations are made for an optimized assembly process flow.

Assembly and Scaling Challenges for 2.5D IC

2014 ◽  
Vol 2014 (1) ◽  
pp. 000606-000611 ◽  
Author(s):  
Liang Wang ◽  
Charles G. Woychik ◽  
Guilian Gao ◽  
Scott McGrath ◽  
Hong Shen ◽  
...  
Keyword(s):  
High Volume ◽  
Thermal Dissipation ◽  
Test Vehicle ◽  
Advantages And Disadvantages ◽  
Interconnect Delay ◽  
Critical Areas ◽  
Temporary Bonding ◽  
Advanced Packaging ◽  
Computing Performance ◽  
Material Process

2.5D technology is gaining acceptance in the industry and an increasing number of products are beginning to enter volume manufacturing. As with all interconnect technologies, the key metrics driving the transition include higher computing performance, lower power consumption, smaller form factor, increased bandwidth and reduced latency (interconnect delay). In order to transition from today's low volumes to High Volume Manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput) and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process and integration choices. With these concerns as a backdrop, our paper will discuss our approach to optimizing 2.5D assembly for HVM. We will begin with a review of our test vehicle and our overall choices of substrate, interposer and die dimensions. Three different 2.5D assembly approaches that have been investigated at Invensas for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. We will present our results from critical areas including temporary bonding, thermo-compression bonding, mass reflow, thin wafer/die handling, flux, underfill and molding. This paper will present our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In addition, we will also provide the results of our cost modeling work. We will finish by making recommendations for an optimized assembly process flow.

Control of 3D IC process steps by optical metrologies

2015 ◽  
Vol 2015 (1) ◽  
pp. 000479-000485
Author(s):  
G. Fresquet ◽  
D. Le Cunff ◽  
Th. Raymond ◽  
D. K. de Vries
Keyword(s):  
Small Diameter ◽  
Optical Metrology ◽  
Wafer Surface ◽  
Data Set ◽  
Process Step ◽  
Deep Reactive Ion Etching ◽  
Full Field ◽  
Process Implementation ◽  
Temporary Bonding ◽  
Advanced Packaging

This paper evaluates various optical metrology techniques for in-line control of the uniformity of 3D stacked structures. Advanced packaging technologies are rapidly evolving and 3D architectures require very well controlled process steps. Optical metrology techniques are now used for TSV but also for interconnect processing. In engineering mode, at the process implementation step, these techniques must be evaluated and then used to get uniform and repeatable processes. Among the 3D TSV Via middle process flow, the temporary bonding, wafer thinning and TSV reveal are key 3D process steps to get a uniform backside copper nail signature. High aspect ratio TSV are etched in Front End of the line and deep reactive ion etching systems generates radial non uniformities signatures. The wafer backside processing challenge consists in compensating this issue among the entire wafer surface. In this paper, all these process steps were characterized in order to quantify their specific intra-wafer dispersion signature .of the related key parameters. Cross correlation between the various intra-wafer process step signatures was then analyzed to verify the data set consistency and several process parameters analyzed to get a simple model. This model was then used to get a very uniform copper nail signature. For small diameter TSV and corresponding copper nails, a comparison has been done between full field OCT and confocal chromatic techniques.

Advanced Acoustic Micro Imaging Applications: Deciphering Multiple Acoustic Echoes and Reflections

2004 ◽  
Author(s):  
Andrew J. Komrowski ◽  
Luis A. Curiel ◽  
Daniel J. D. Sullivan ◽  
Quang Nguyen ◽  
Lisa Logan-Willams
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
New Technologies ◽  
Electronic Packages ◽  
Advanced Packaging ◽  
Ic Package ◽  
Non Destructive

Abstract The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.

scholarly journals A Hermetic Advanced Packaging Solution for Optical Devices Using a Glass-Capping Technology on Wafer-Level

2009 ◽  
Vol 1 (1) ◽  
pp. 1527-1530
Author(s):  
S. Maus ◽  
U. Hansen ◽  
J. Leib ◽  
M. Töpper
Keyword(s):  
Optical Devices ◽  
Wafer Level ◽  
Advanced Packaging
Sign in / Sign up

Export Citation Format

Share Document