Wafer Thinning for Advanced Packaging Applications

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-26
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Scott Kroeger
Keyword(s):  
Low Cost ◽  
High Volume ◽  
Alternative Methods ◽  
Critical Element ◽  
Wafer Level ◽  
Temporary Bonding ◽  
Scale Down ◽  
Advanced Packaging ◽  
Wafer Thinning ◽  
Etch Profile

Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. The high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry. Lower-cost advanced packaging concepts have been developed and are now in high-volume production. Recently, alternative methods for exploiting the z-direction have turned to variations of Fan-Out Wafer Level Packaging (FOWLP), which do not include TSVs. In many of these concepts there is a need to thin the wafer to remove all of the silicon while being selective and not etching a variety of other films that include oxides, nitrides, and metals. In addition, there can be temporary bonding adhesives and mold compounds encapsulating the chips; these must remain undamaged. Another critical element of a successful process is the ability to control the profile of the silicon etch to provide uniform removal. The single wafer wet etching techniques and advanced process control developed for TSV Reveal are applicable to these structures and provide a low-cost alternative to CMP and Plasma processes. To successfully execute the process, several characteristics must be met: the silicon overburden depth and profile need to be determined, the overburden thinning etch needs a fast sculpting etchant, and the finishing etchant needs to be selective to materials that will be exposed at the completion of the etch. In addition, the tool used to perform this sequence needs to have the correct metrology capability, along with properly chosen etchants. Similarly, it is not sufficient to know the required etch profile, the software must be able to execute a unique etch profile for each wafer. In this fashion, the finishing etch time can be kept to a minimum. This is important, as many of the selective etchants have a slow etch rate, and adhesives used do not always hold up to exposure to the chemistries involved for long periods. This paper discusses the use of wet etch wafer thinning processes for new FOWLP applications.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

Packaging Materials for 2.5/3D Technology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
High Yield ◽  
Wafer Level ◽  
Reflow Process ◽  
Thermal Compression ◽  
Conductive Films ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).

Assembly Equipment Requirements for Next Generation Advanced Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann
Keyword(s):  
Capital Investment ◽  
Flip Chip ◽  
High Volume ◽  
Electrical Performance ◽  
Wafer Level ◽  
Considerable Uncertainty ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
The Impact ◽  
3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-15
Author(s):  
Hong Xie ◽  
Daquan Yu ◽  
Zhenrui Huang ◽  
Zhiyi Xiao ◽  
Li Yang ◽  
...  
Keyword(s):  
Form Factor ◽  
High Speed ◽  
Low Cost ◽  
High Density ◽  
Wafer Level ◽  
Small Form ◽  
Wafer Level Packaging ◽  
Temporary Bonding ◽  
Small Form Factor ◽  
Si Wafer

The growing and diversifying system requirements have continued to drive the development of a variety of new package technologies and configurations: small form factor, low weight, low profile, high pin count and high speed and low cost. Embedded chip in EMC, also called fan-out wafer-level packaging (FOWLP), has been used in various products such as baseband, RF (radio frequency) transceiver, and PMICs (power management ICs). Currently, INFO technology developed by TSMC®, NANIUM® were in mass production for 3D integration for processor and memory, which inspires other packaging foundries to develop their own embedded FOWLP for the forecasted explosive growth of this market in the next few years. There are a number of challenges for FOWLP. For process point of view, temporary bonding and de-bonding are required. EMC wafers are difficult to handle due to its large warpage driven by the big CTE difference between the Si and molding material. In addition, the manufacturing of fine pitch RDL on EMC surface is also difficult. In this paper, the concept of wafer level embedded Si Fan-Out (eSiFO) technology was introduced and the development progress was reported. For eSiFO, cavities with certain depth were formed by Si dry etch. Then device dies were thinned to designed thickness. The dice were then placed into the cavities and bonded by the attached film on the bottom of the dice. A reconstructed wafer was formed. The micro gap between the chip and sidewall of the cavity as well as the surface of the reconstructed wafer were filled by dry film using vacuum process. Next, the pads were opened, followed RDL fabrication, repassivation, BGA, wafer thinning and dicing. Finally, an eSiFO package was fabricated. There are a number of advantages for eSiFO technology. There is nearly no warpage since the Si was used as reconstruct substrate. The process is relatively simple since no molding, temporary bonding and de-bonding are required. RDL manufacturing is easier on Si wafer vs with molding compounds and can achieve high density routing. Furthermore, it can provide small form factor since the thinning of wafer is the last step. To prove the concept of eSiFO, a 3.3 x 3.3mm package with 50 BGA bumps at 400μm pitch was fabricated. The device wafer was thinned to 100μm. The die size is 1.96 × 2.36mm with pad pitch at about 90μm. The depth of the cavities on 8 in. wafer formed by Bosch process on bare Si wafer was 107μm with 8μm variation. The length and width of Si cavities is 20μm larger than die size. In the package, there is one layer Cu RDL with thickness of 3μm, minimum line width of 13.72μm. The BGA ball diameter is 280μm. All the processes were evaluated and the results showed such packages can be produced. Reliability tests including THS, T/C, HTS and HAST were carried out and no failure issue was observed. Mechanical simulation was used to analyze the stress distribution during TC test and the results showed the maximum stress was located at the RDL near the UBM. In summary, a low cost wafer level fan out technology using reconstructed Si wafer was developed. The process is simple without molding, temporary bonding and de-bonding. The reliability tests of test vehicles proved that such package is reliable. The newly developed eSiFO technology can be widely used for chips requiring fan-Out, small form factor and high density interconnects.

Microfabrication and Packaging Process for a Single-Chip Position, Navigation, and Timing System

2017 ◽  
Vol 2017 (1) ◽  
pp. 000208-000214 ◽  
Author(s):  
Junjun Huan ◽  
Vamsy P. Chodavarapu ◽  
George Xereas ◽  
Charles Allan
Keyword(s):  
Inertial Sensors ◽  
Low Cost ◽  
Autonomous Systems ◽  
Pressure Sensors ◽  
Single Crystal Silicon ◽  
High Volume ◽  
Leak Rate ◽  
Single Chip ◽  
Wafer Level ◽  
Crystal Silicon

Abstract The Global Positioning System (GPS) is the primary means of Positioning, Navigation, and Timing (PNT) for most civilian and military systems and applications. The rapid growth in autonomous systems has created a widespread interest in self-contained Inertial Navigation System (INS) for precise navigation and guidance in the absence of GPS. The microscale PNT systems need both specialized and low cost fabrication technologies to cost effectively bring these technologies to market. We describe an ultra-clean (low leak rate) wafer-level vacuum encapsulation microfabrication process of Micro-Electro-Mechanical Systems (MEMS) based sensors and devices. Using this process we have fabricated inertial sensors, frequency reference resonators, and pressure sensors. In addition to providing excellent resistance to shock and vibration, this combined microfabrication and packaging method would allow the use of high volume low cost plastic packaging at the device level. The microfabrication process is an 8” wafer process based on high aspect ratio bulk micromachining of a 30 μm thick single-crystal silicon device layer that is vacuum encapsulated at 10 mTorr between two silicon wafers with the demonstrated leak rate of only 6.5 × 10−18 atm cm3/s.

Chip Last Fan Out as an Alternative to Chip First

2015 ◽  
Vol 2015 (1) ◽  
pp. 000245-000250 ◽  
Author(s):  
Scott Chen ◽  
Simon Wang ◽  
Coltrane Lee ◽  
Adren Hsieh ◽  
John Hunt ◽  
...  
Keyword(s):  
Low Cost ◽  
Smart Phone ◽  
High Volume ◽  
Smart Phones ◽  
Portable Devices ◽  
Wafer Level ◽  
Packaging Technology ◽  
Two Factors ◽  
The Cost ◽  
Technology Nodes

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, and they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), and system in package (SIP) being widely used in these smart phones & mobile devices.. Fan out WLCSP (FOWLP) has great potential to be the next new package for the smart phone mobility application. Two factors have driven fan out WLCSP (FOWLP) package technology in the last few years. The first is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solder ball interconnects. The second and potentially more important factor relates to the demand of the market for more functions. Not all silicon functionality benefits from these advanced nodes, and merely adds to the cost of the die. This has driven the designers to partitioning of desired functionality into multiple die, which in turn requires effective interconnection of these separate die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). Up to date FOWLP used chip first processing, in which the bare die was molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a new alternative to chip first FOWLP, an alternative which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package has been in production in ASE for over a year, and uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented. We have designated this package structure “Fan Out Chip Last Package (FOCLP)” For higher end applications we will show the ability to use a high density substrate process for use in more demanding chip last fan out packages

Embedded solutions: Fan-out and Embedded Die Packages market and technology trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000235-000238
Author(s):  
Jérôme Azémar
Keyword(s):  
Supply Chain ◽  
Business Models ◽  
Low Cost ◽  
High Volume ◽  
Added Value ◽  
System Level ◽  
Wafer Level ◽  
High Expectations ◽  
Interesting Approach ◽  
Pcb Manufacturing

Embedded packages are nowadays not anymore just an interesting approach for some specific application. Benefiting from 3D TSV high cost, and consequently delays, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players. In this presentation we will focus on two main types of embedded packages, those that are most of interest at the moment: Fan-Out and Embedded Dies packages. The principle of Fan Out technology is to embed products in a molded compound and allow redistribution layers pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and Stats ChipPAC using eWLB type of Fan-Out. Market for Fan-Out packages in 2014 almost reached $200M and a 20% growth for the coming years is expected. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like SPIL or J-Devices are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The principle of Embedded die packages has the same purpose of promoting high integration due to placing chips within the substrate but with a different approach: Embedding is done in laminate substrates. This process is pushed by PCB manufacturers such as AT&S and could create a new supply chain with new players. One of the main advantages is to use a mature and cheap manufacturing chain created for PCB manufacturing and then having low cost for a technology that would allow a good integration and access to both sides of the chips easily. On the other hand, Embedded Die technologies are still waiting for a high volume project that shall be coming once higher yield, better resolution and clarification of the supply chain will be achieved. In this presentation we will describe what the strategies to reach that goal are. Both technologies seem to be competing but are actually complementary and often targeting different markets. Key customers already qualified them and will open the gates for the fast growing packaging market. The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out and embedded die packaging approaches by applications, business models and major players will be reviewed.

Transition From MEMS Technology to Nanofabrication

2007 ◽  
Author(s):  
T. Glinsner ◽  
P. Lindner ◽  
P. Kettner ◽  
H. Kirchberger
Keyword(s):  
Nanoimprint Lithography ◽  
Low Cost ◽  
High Volume ◽  
Laboratory Research ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Industrial Processing ◽  
The Past ◽  
Mems Technology

The successful commercialization of Micro-Electro-Mechanical Systems (MEMS) from R&D to off-the-shelf products and systems has evolved from laboratory research to reliable and low cost industrial processing methods over the past 20 years. Standardization, infrastructure, roadmaps and industrial associations have been deemed key contributors for a successful transition and adaptation of microelectronics fabrication techniques to a specific nature of manufacturing MEMS devices resulted in turn key solutions for low cost, high yield and high volume wafer level processing. The need for smaller feature sizes as well as low cost manufacturing solutions has lead to significant improvements of the classical optical lithography in the past two decades following Moore’s law. Alternative patterning techniques are under development worldwide for producing patterns in the nm-range. There are similarities between MEMS and Nanofabrication requirement that allow for transitioning standardized and reliable processing technology from wafer bonding to hot embossing and from wafer level packaging to μ-CP and UV-based Nanoimprint Lithography.

Development of skills and tools for micro opto-electrical integration on wafer level

2018 ◽  
Vol 2018 (1) ◽  
pp. 000652-000654
Author(s):  
Saskia Schröder ◽  
Vanessa Stenchly ◽  
Hans-Joachim Quenzer ◽  
Wolfgang Reinert
Keyword(s):  
Augmented Reality ◽  
Low Cost ◽  
Laser Diodes ◽  
High Volume ◽  
Light Sources ◽  
Optical Bench ◽  
Wide Spread ◽  
Wafer Level ◽  
Heat Spreader ◽  
New Approach

Abstract New devices for a digital lifestyle like augmented reality (AR) glasses may find their wide spread use only if consumer relevant pricing can be achieved. Low cost RGB-light sources are a key element for AR. assembly productivity for these micro opto-electrical RGB-light sources and a further reduction in their package dimensions. We present our new approach to build miniature RGB-light sources on structured silicon wafers and elaborate the required skill set and our future process infrastructure based on our existing high volume capable optical packaging platform. The platform provides an optical bench with integrated heat spreader and emission windows enabling miniature hermetic housing for laser diodes assemblies on 8″ wafers.

Current status and future prospects of panel level packaging

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000707-000750
Author(s):  
Santosh Kumar ◽  
Amandine Pizzagalli ◽  
Dave Towne ◽  
Thibault Buisson ◽  
Andrej Ivankovic ◽  
...  
Keyword(s):  
Semiconductor Industry ◽  
High Volume ◽  
Current Status ◽  
Flat Panel Display ◽  
Future Prospects ◽  
Wafer Level ◽  
Commercial Development ◽  
Economy Of Scale ◽  
Wafer Level Packaging ◽  
Advanced Packaging

Demand of lower cost with higher performances has driven the semiconductor industry to develop innovative solutions. One of the new approaches to reduce the overall cost is to switch from wafer to larger size panel format. The panel infrastructure has gained considerable interest from the semiconductor industry and is certainly a promising market due to its cost advantages and economy of scale benefits. Panel level manufacturing has the potential to leverage the knowledge and infrastructure of wafer level packaging as well as PCB / flat panel display / photovoltaic industries. We have identified six key packaging platforms which can be processed on larger surface (rectangular/square) such as FOWLP panel, organic interposer, glass panel interposer, hybrid interposer, embedded die as well as coreless substrate. Over the past years, it's become clear that some panel packages choices will be more suitable than others for successful commercial development. The equipment infrastructure within the advanced packaging supply chain today is mainly based on processing 300mm round wafers. However, to process larger surface, new equipment and optimized materials are required. The key question raised is when the panel industry will take off and how will it evolve? Are the supply chains ready to move to the panel scale manufacturing? What are the challenges / issues involved for the panel adoption to high volume manufacturing? This paper will try to answer these questions and discuss about the current status and future prospects of panel level packaging.

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