Pattern Loading Effect Optimization of BEOL Cu CMP in 14nm Technology Node

AbstractStudies of the wafer edge uniformity step by step, from hard mask deposition, reactive ion etch, electroplating to post Cu CMP had been done using scanning electron microscopy (SEM) measurements, showed that the major wafer non-uniformity comes from the Cu CMP step. Improvement of Cu CMP edge uniformity had been achieved through engineering of platen 1 using real time profile control as well as CMP head zone pressure adjustment and platen 3 slurry optimizations

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Root Cause Analysis for Pin Leakage

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0217 ◽

2016 ◽

Author(s):

Zhigang Song ◽

Jochonia Nxumalo ◽

Manuel Villalobos ◽

Sweta Pendyala

Keyword(s):

Failure Analysis ◽

Root Cause Analysis ◽

Advanced Technology ◽

Process Step ◽

Cause Analysis ◽

Hard Mask ◽

Technology Node ◽

Root Cause ◽

Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

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Insight into the tannic acid-based modular-assembly strategy based on inorganic–biological hybrid systems: a material suitability, loading effect, and biocompatibility study

Materials Chemistry Frontiers ◽

10.1039/d0qm00887g ◽

2021 ◽

Author(s):

Xiaoning Ren ◽

Panqing Yin ◽

Jun Liang ◽

Xiangjian Liu ◽

Wugen Zhan ◽

...

Keyword(s):

Hybrid Systems ◽

Tannic Acid ◽

Modular Assembly ◽

Loading Effect ◽

Assembly Strategy ◽

Biocompatibility Study ◽

Insight Into

The tannic acid-based modular-assembly strategy for building inorganic–biological hybrids is studied regarding the aspects of the material suitability, loading effect, and biocompatibility.

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Decreasing the Loading Effect of the TVS Diode Using a Transmission Line for RF and Microwave Applications

IEEE Letters on EMC Practice and Applications ◽

10.1109/lemcpa.2020.3035785 ◽

2021 ◽

Vol 3 (1) ◽

pp. 29-33

Author(s):

Emad Zia Khodadadian ◽

Mojtaba Joodaki

Keyword(s):

Transmission Line ◽

Loading Effect ◽

Microwave Applications

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CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽

10.3390/electronics10040443 ◽

2021 ◽

Vol 10 (4) ◽

pp. 443

Author(s):

Mihaela-Daniela Dobre ◽

Philippe Coll ◽

Gheorghe Brezeanu

Keyword(s):

Electrostatic Discharge ◽

New Technology ◽

Test Chip ◽

Technology Node ◽

Ground Resistance ◽

Maximum Resistance ◽

Device Model ◽

Protection Method ◽

Esd Protection ◽

Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

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