A Single-Layer Solution with Laser Debonding Technology for Temporary Bond/Debonding Applications in Wafer-Level Packaging

Author(s):  
Xiao Liu ◽  
Lisa Kirchner ◽  
Luke Prenger ◽  
Wenkai Cheng ◽  
Rama Puligadda
Author(s):  
Luke Prenger ◽  
Xiao Liu ◽  
Qi Wu ◽  
Rama Puligadda

Multifunctional materials are a relatively new topic in the semiconductor industry for wafer-level packaging (WLP). With the increase in processing steps and the emergence of more advanced technologies, the use of multifunctional materials will become a more integral part in the future of temporary bonding and debonding (TB/DB) as well as other advanced packaging applications. One approach to multifunctional material design incorporates adhesive and laser release attributes in one material layer. Although this is similar to a thermal release material, it has greater thermal capabilities due to its ability to be cured and undergo laser debond. Many advantages may be obtained by combining a curable adhesive and laser release layer into one material. One of the greatest advantages is the reduction in overall processing time and steps required to bond wafer pairs as well as the reduction of chemical waste, due to the use of one material compared to two or more materials which significantly reduces the cost of ownership. Curable adhesive single layer systems offer access to higher temperatures with less material flow from the curable layer, strong adhesion for high stress applications where wafers can delaminate or spontaneously debond when using multilayer mechanically debonding systems such as Fan-Out Wafer Level Packaging (FOWLP), and offer lower wafer stress and warpage due to fewer material interfaces within the bonded wafer pairs causing less potential mismatch of materials coefficient of thermal expansion(CTE). Some challenges with this concept stem from the concern of the cleanability of a curable layer and potential laser damage to the device. In order to wet clean a curable layer, which is usually very solvent resistant due to the crosslinked nature, requires harsh solvent based solutions (that may contain either strong acid or base, require long cleaning time, and high temperature). This study will address all of the aforementioned challenges and includes the developmental advancements in material designs that resulted in the creation of new multifunctional materials. These multifunctional materials have been designed to be thermally curable, prevent material reflow of the bonding layer at higher temperatures, while still remaining wet cleanable without the use of harsh chemicals and long times. As with any material that utilize laser release methods there are concerns about device damage from laser energy penetrating to the device but multifunctional materials address this in two ways: they offer high absorbance of the laser energy at all commercially available laser tool wavelengths and they can be utilized as a thicker film as they act as the bonding layer as well. By overcoming their challenges, they will minimize the cost of ownership while driving advancement in future materials and processing.


2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka

Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.


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