Material Design Advancement Create Multifunctional Materials for Single-Layer Bonding and Debonding

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000908-000931
Author(s):  
Luke Prenger ◽  
Xiao Liu ◽  
Qi Wu ◽  
Rama Puligadda
Keyword(s):  
Laser Energy ◽  
Semiconductor Industry ◽  
Single Layer ◽  
Material Design ◽  
Bonding Layer ◽  
Multifunctional Materials ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Cost Of Ownership ◽  
The Cost

Multifunctional materials are a relatively new topic in the semiconductor industry for wafer-level packaging (WLP). With the increase in processing steps and the emergence of more advanced technologies, the use of multifunctional materials will become a more integral part in the future of temporary bonding and debonding (TB/DB) as well as other advanced packaging applications. One approach to multifunctional material design incorporates adhesive and laser release attributes in one material layer. Although this is similar to a thermal release material, it has greater thermal capabilities due to its ability to be cured and undergo laser debond. Many advantages may be obtained by combining a curable adhesive and laser release layer into one material. One of the greatest advantages is the reduction in overall processing time and steps required to bond wafer pairs as well as the reduction of chemical waste, due to the use of one material compared to two or more materials which significantly reduces the cost of ownership. Curable adhesive single layer systems offer access to higher temperatures with less material flow from the curable layer, strong adhesion for high stress applications where wafers can delaminate or spontaneously debond when using multilayer mechanically debonding systems such as Fan-Out Wafer Level Packaging (FOWLP), and offer lower wafer stress and warpage due to fewer material interfaces within the bonded wafer pairs causing less potential mismatch of materials coefficient of thermal expansion(CTE). Some challenges with this concept stem from the concern of the cleanability of a curable layer and potential laser damage to the device. In order to wet clean a curable layer, which is usually very solvent resistant due to the crosslinked nature, requires harsh solvent based solutions (that may contain either strong acid or base, require long cleaning time, and high temperature). This study will address all of the aforementioned challenges and includes the developmental advancements in material designs that resulted in the creation of new multifunctional materials. These multifunctional materials have been designed to be thermally curable, prevent material reflow of the bonding layer at higher temperatures, while still remaining wet cleanable without the use of harsh chemicals and long times. As with any material that utilize laser release methods there are concerns about device damage from laser energy penetrating to the device but multifunctional materials address this in two ways: they offer high absorbance of the laser energy at all commercially available laser tool wavelengths and they can be utilized as a thicker film as they act as the bonding layer as well. By overcoming their challenges, they will minimize the cost of ownership while driving advancement in future materials and processing.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Fan-in WLP: Technology and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000067-000072 ◽  
Author(s):  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
A. Pizzagalli ◽  
J. Azemar ◽  
...  
Keyword(s):  
Flip Chip ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
Current Status ◽  
Wafer Level ◽  
New Era ◽  
Device Scaling ◽  
Depth Analysis ◽  
Application Diversification ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

Integrated Microsystems

2012 ◽  
Vol 81 ◽  
pp. 55-64 ◽  
Author(s):  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wireless Systems ◽  
Tactile Sensor ◽  
Wafer Level ◽  
Micro Electro Mechanical Systems ◽  
Silicon Chips ◽  
Open Collaboration ◽  
Wafer Level Packaging ◽  
Integrated Microsystems ◽  
Safety Systems ◽  
The Cost

Technology called MEMS (Micro Electro Mechanical Systems) or microsystems are heterogeneous integration on silicon chips and play important roles as sensors. MEMS as switches and resonators fabricated on LSI are needed for future multi-band wireless systems. MEMS for safety systems as event driven tactile sensor network for nursing robot are developed. Wafer level packaging for MEMS and open collaboration to reduce the cost for the development are discussed.

M-Series with Adaptive Patterning for High-Yield Fan-Out SIP

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000751-000773
Author(s):  
Craig Bishop ◽  
Suresh Jayaraman ◽  
Boyd Rogers ◽  
Chris Scanlan ◽  
Tim Olson
Keyword(s):  
New Technology ◽  
Minimum Size ◽  
High Yield ◽  
Wafer Level ◽  
Design Rules ◽  
Optical Scanner ◽  
Wafer Level Packaging ◽  
And Performance ◽  
The Cost ◽  
Semiconductor Chips

Fan-Out Wafer Level Packaging (FOWLP) holds immediate promise for packaging semiconductor chips with higher interconnect density than the incumbent Wafer Level Chip Scale Packaging (WLCSP). FOWLP enables size and performance capabilities similar to WLCSP, while extending capabilities to include multi-device system-in-packages. FOWLP can support applications that integrate multiple heterogeneously processed die at lower cost than 2.5D silicon interposer technologies. Current industry challenges with die position yield after die placement and molding result in low-density design rules and the high-cost of accurate die placement. Efficiently handling die shift is essential for making FOWLP cost-competitive with other technologies such as FCCSP and QFN. This presentation will provide an overview of Adaptive Patterning, a new technology for overcoming variability of die positions after placement and molding. In this process, an optical scanner is used to measure the true XY position and rotation of each die after panelization. The die measurements are then fed into a proprietary software engine that generates a unique pattern for each package. The resulting patterns are dispatched to a lithography system, which dynamically implements the unique patterns for all packages within a panel. For system-in-packages, this process offers a unique advantage over a fixed pattern: each die shift can be handled independently. With a fixed pattern, the design tolerances need to be large enough for all die to shift in opposing directions, otherwise yield loss in incurred. With Adaptive Patterning, vias and RDL features remain at minimum size and are matched to the measured die shift. The die-to-die interconnects are dynamically generated and account for the unique position of each die. Thus, Adaptive Patterning retains the same high-density design rules regardless of how many die are in a package. Adaptive Patterning provides the capability to use high-throughput die placement to drive down cost, while enabling higher-density system-in-package interconnect. With this technology the industry can finally realize the cost, flexibility, and form factor benefits of FOWLP.

Self Priming Low Stress Aqueous Developable Benzocyclobutene (AD-BCB) Photodielectric Materials for Advanced Wafer Level Packaging

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000679-000697
Author(s):  
Hua Dong ◽  
Greg Prokopowicz ◽  
Bob Barr ◽  
Joe Lachowski ◽  
Jeff Calvert ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
High Reliability ◽  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Film Stress ◽  
Wafer Level ◽  
Adhesion Promoter ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
New Formulation

As the semiconductor industry drives to more functionality in smaller and lighter devices, it requires new materials to meet the changing requirements of new and more advanced chip designs and packaging solutions. Photoimagable polymeric dielectric materials are a key building block for wafer level packaging (WLP); these include polyimide (PI), polybenzoxazole (PBO), acrylics, silicones, epoxy-phenolics and benzocyclobutene (BCB). Because of low copper diffusion, low temperature curing, high reliability and low moisture adsorption, BCB was the platform chosen for modification. In this work, we will focus on the development of self priming, low stress, aqueous developable version of BCB, known as AD-BCB. This new photodielectric material has improved mechanical properties of <25MPa film stress value and >28% elongation while maintaining good post develop and post cure adhesion on various substrates including silicon, silicon oxide, silicon nitride, copper, aluminum and epoxy molding compound. Elongation is significantly increased for this positive tone, aqueous developable, photodielectric materials, while film stress and wafer bow are significantly reduced. In addition, this new formulation is self priming and does not require a spin-on adhesion promoter. The material can be cured at as low as 200 °C with lithographic feature size of <10 μm and dielectric constant of 3.0.

Fan-Out Packaging: Technologies and market trends

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-35 ◽  
Author(s):  
Jerome Azemar
Keyword(s):  
Cost Reduction ◽  
Business Models ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
High Volume ◽  
Main Trend ◽  
Wafer Level ◽  
Device Scaling ◽  
Application Processor ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level solution aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. In this work we will focus on Fan-Out packaging, an embedded package of most interest at the moment. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature for several years thanks to high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, and with many other developments from OSATs and an aggressive technology from TSMC (inFO). 2016 was a turning point for the Fan-Out market with Apple A1O application processor being packaged using TSMC solution. This partnership changed the game and may create a trend of acceptance of Fan-Out packages for complex applications. The market for Fan-Out packages in 2016 already reached $500M, with potential breakthrough events in store in 2017 that could make the market reach $2B in 2020. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, capable of embedding complex ICs, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC being the first example, foundries too could look at the OSATs reserved market through wafer-level packages, Samsung's reaction being interesting to follow. Each player has its own view on how to gain market share and meet the technical and financial challenges associated to Fan-Out packaging such as cost reduction, yield improvement, die shift… This work brings analysis of the strategies and offers of main players involved and describes potential success scenarios for them. It also helps to define what is Fan-Out Packaging and what are the different products and platforms, player per player, avoiding confusion already visible in the industry where many players call their solution a “Fan-Out” to benefit from the buzz created by Apple despite having significant differences from one to another (chip-first, chip-last, face-up, face-down, etc…). As package price represents the final verdict, carrier size evolution is also an important topic, both for wafers and panels, since it can help to drastically reduce the cost. This work shows that the main trend is still to keep wafer carriers but some players are already investing and developing panel-based solution and we expect volume production soon. While end-customers are pushing for a switch to panel, numerous challenges are limiting its widespread though. This work describes technical, economic and maturity challenges associated to panel manufacturing. Overall, the presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

The history of the standard for the calculation of cost of ownership in the semiconductor industry

2018 ◽  
Vol 24 (1) ◽  
pp. 62-82
Author(s):  
Maximilian Sandholzer ◽  
Marc Wouters
Keyword(s):  
Research And Development ◽  
Management Accounting ◽  
Semiconductor Industry ◽  
Standard Setting ◽  
Technical Standards ◽  
Cost Of Ownership ◽  
History Of ◽  
The Cost

The semiconductor industry is one of very few industries to have a standard for management accounting, and this concerns a method for calculating the cost of ownership (COO). This research investigates the history of the development of the COO standard, starting from the late 1980s and stretching to the mid-1990s, and explores the circumstances under which this development occurred. We find that the development and revision activities for COO built on complementary conditions, such as industry organizations, networks of professionals, and standard-setting procedures, which had been established for cooperation in research and development and for the development of technical standards. We suggest that these factors may explain the absence of standards in management accounting in many other settings.

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