A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism

2010 ◽  
Author(s):  
Marc de Kruijf ◽  
Shuou Nomura ◽  
Karthikeyan Sankaralingam
Keyword(s):  
Unified Model ◽  
Fault Recovery ◽  
Technology Scaling ◽  
Recovery Mechanism ◽  
Cmos Design ◽  
Timing Speculation ◽  
Impact Of Technology ◽  
Design Style ◽  
The Impact

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

The Impact of Technology Scaling for RF Complementary Metal–Oxide–Semiconductor

2009 ◽  
Vol 48 (1) ◽  
pp. 011208
Author(s):  
Eiji Morifuji ◽  
Hideki Kimijima ◽  
Kenji Kojima ◽  
Masaaki Iwai ◽  
Fumitomo Matsuoka
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Technology Scaling ◽  
Impact Of Technology ◽  
The Impact

Reliability and Performance Analysis of Architecture-Based Software Implementing Restarts and Retries Subject to Correlated Component Failures

2015 ◽  
Vol 25 (08) ◽  
pp. 1307-1334 ◽  
Author(s):  
Xiao-Dan Li ◽  
Yong-Feng Yin ◽  
Lance Fiondella
Keyword(s):  
Software Reliability ◽  
High Reliability ◽  
Experimental Studies ◽  
Software Systems ◽  
Fault Recovery ◽  
Recovery Mechanism ◽  
Software Models ◽  
And Performance ◽  
Component Failures ◽  
The Impact

High reliability and performance are essential attributes of software systems designed for critical real-time applications. To improve the reliability and performance of software, many systems incorporate some form of fault recovery mechanism. However, contemporary models of software reliability and performance rarely consider these fault recovery mechanisms. Another notable shortcoming of many software models is that they make the simplifying assumption that component failures are statistically independent, which disagrees with several experimental studies that have shown that the failures of software components can exhibit correlation. This paper presents an architecture-based model of software reliability and performance that explicitly considers a two-stage fault recovery mechanism implementing component restarts and application-level retries. The application architecture is characterized by a Discrete Time Markov Chain (DTMC) to represent the dynamic branching behavior of control between the components of the application. Correlations between the component failures are computed with an efficient numerical algorithm for a multivariate Bernoulli (MVB) distribution. We illustrate the utility of the model through a case study of an embedded software application. The results suggest that the model can be used to quantify the impact of software fault recovery and correlated component failures on application reliability and performance.

Standard Cell-Based Low Power Embedded Controller Design

2015 ◽  
Vol 24 (06) ◽  
pp. 1550077
Author(s):  
Borisav Jovanović ◽  
Milunka Damnjanović ◽  
Predrag Petković ◽  
Vančo Litovski
Keyword(s):  
Low Power ◽  
Controller Design ◽  
Design Flow ◽  
Standard Cell ◽  
Technology Scaling ◽  
Cell Library ◽  
Ip Blocks ◽  
Comparison Of The Results ◽  
Impact Of Technology ◽  
The Impact

Microcontrollers represent unavoidable parts of state-of-the-art system-on-chips (SoCs) and they are widely embedded as IP blocks. This paper describes design steps and the application of available low-power techniques, to the design of a microcontroller IP core with 8051 instruction set, based on a prescribed standard cell libraries. Choice of the technology node and the cell library supplier is a design challenge that was considered and conclusions reached. The necessary steps of microcontroller design flow are presented which enable power reduction at several abstraction levels. An optimal microcontroller was designed to be embedded in various SoCs. The goal was to get energy-efficient microcontroller operation in applications which don't require intensive data processing. The impact of technology scaling on microcontroller energy efficiency is considered by comparison of the results obtained from implementations in three standard cell technologies. Moreover, power dissipation models are created which allow for microcontroller's power estimation in low throughput sensors networks applications.

scholarly journals Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

2019 ◽  
Vol 35 (3) ◽  
pp. 303-315
Author(s):  
Mahroo Zandrahimi ◽  
Philippe Debaud ◽  
Armand Castillejo ◽  
Zaid Al-Ars
Keyword(s):  
Low Cost ◽  
Delay Testing ◽  
Technology Scaling ◽  
Impact Of Technology ◽  
The Impact
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