High efficiency and smooth transition buck-boost converter for extending battery life in portable devices

2009 ◽  
Author(s):  
Ping-Ching Huang ◽  
Wei-Quan Wu ◽  
Hsin-Hsin Ho ◽  
Ke-Horng Chen
Keyword(s):  
High Efficiency ◽  
Boost Converter ◽  
Smooth Transition ◽  
Battery Life ◽  
Portable Devices

scholarly journals A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-7
Author(s):  
Hou-Ming Chen ◽  
Robert C. Chang ◽  
Kuang-Hao Lin
Keyword(s):  
High Efficiency ◽  
Power Conversion ◽  
Cmos Technology ◽  
Pulse Frequency ◽  
Boost Converter ◽  
Battery Life ◽  
Pulse Frequency Modulation ◽  
Load Range ◽  
Load Current ◽  
The Cost

This paper presents a high-efficiency monolithic dc-dc PFM boost converter designed with a standard TSMC 3.3/5V 0.35 μm CMOS technology. The proposed boost converter combines the parallel power MOS technique with pulse-frequency modulation (PFM) technique to achieve high efficiency over a wide load current range, extending battery life and reducing the cost for the portable systems. The proposed parallel power MOS controller and load current detector exactly determine the size of power MOS to increase power conversion efficiency in different loads. Postlayout simulation results of the designed circuit show that the power conversion is 74.9–90.7% efficiency over a load range from 1 mA to 420 mA with 1.5 V supply. Moreover, the proposed boost converter has a smaller area and lower cost than those of the existing boost converter circuits.

Selectable Output Voltage High Efficiency Boost Converter

2018 ◽  
Vol 27 (11) ◽  
pp. 1850178 ◽  
Author(s):  
Li-Ye Cheng ◽  
Chen Sun ◽  
Zhen-Wei Zhou
Keyword(s):  
High Efficiency ◽  
Input Voltage ◽  
Boost Converter ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Portable Devices ◽  
Cmos Process ◽  
Transient Time ◽  
Heavy Load ◽  
Light Load

The paper proposed a high efficiency boost converter with constant voltage (CV) and constant current (CC) modes. The selection of CV or CC working mode is based on the requirement, and the transient time from CV to CC mode is 230[Formula: see text][Formula: see text]s. The boost converter is particularly for the use of Li-ion battery portable devices. High efficiency is obtained by sleep/burst mode under light load and pulse width modulation (PWM) mode under heavy load. The quiescent current of the whole chip can be down to 6[Formula: see text][Formula: see text]A when the converter enters the standby mode. The converter has been made of 0.35[Formula: see text][Formula: see text]m complementary metal-oxide semiconductor (CMOS) process. Experimental results show that the peak efficiency is 98.2% at a 1.5[Formula: see text]A output current and a 4.2[Formula: see text]V input voltage.

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

scholarly journals High gain boost converter with modified voltage multiplier for stand alone PV system

2019 ◽  
Vol 14 (1) ◽  
pp. 185
Author(s):  
Getzial Anbu Mani ◽  
A. K. Parvathy
Keyword(s):  
High Efficiency ◽  
Input Voltage ◽  
High Gain ◽  
Boost Converter ◽  
Pv System ◽  
Boost Converters ◽  
Low Input ◽  
Voltage Multiplier ◽  
Photo Voltaic ◽  
Current Ripple

<p>Boost converters of high gain are used for photo voltaic systems to obtain high efficiency. These high gain Boost converters gives increased output voltage for a low input produces high outputs for low input voltage. The High gain boost converters have the following merits. Conduction losses input current ripple and stress across the switches is reduced while the efficiency is increases. The high gain of the converters with the above said merits is obtained by changing the duty cycle of switches accordingly .In this paper a boost converter working with interleaved concept along with a additional Nstage voltage Multiplier has been carried out by simulation using MATLAB/ simulink and the mathematical modeling of various parameters is also done.</p>

scholarly journals High Efficiency Buck-Boost Converter with Three Modes Selection for HV Applications using 0.18 μm Technology

2020 ◽  
Vol 18 (2) ◽  
pp. 137-144
Author(s):  
Fouad Farah ◽  
Mustapha El Alaoui ◽  
Abdelali El Boutahiri ◽  
Mounir Ouremchi ◽  
Karim El Khadiri ◽  
...  
Keyword(s):  
Power Conversion Efficiency ◽  
Conversion Efficiency ◽  
Output Voltage ◽  
High Efficiency ◽  
Power Conversion ◽  
Boost Converter ◽  
Current Control ◽  
Voltage Range ◽  
Operating Modes ◽  
Soft Start

In this paper, we aim to make a detailed study on the evaluation and the characteristics of the non-inverting buck–boost converter. In order to improve the behaviour of the buck-boost converter for the three operating modes, we propose an architecture based on peak current-control. Using a three modes selection circuit and a soft start circuit, this converter is able to expand the power conversion efficiency and reduce inrush current at the feedback loop. The proposed converter is designed to operate with a variable output voltage. In addition, we use LDMOS transistors with low on-resistance, which are adequate for HV applications. The obtained results show that the proposed buck-boost converter perform perfectly compared to others architecture and it is successfully implemented using 0.18 μm CMOS TSMC technology, with an output voltage regulated to 12V and input voltage range of 4-20 V. The power conversion efficiency for the three operating modes buck, boost and buck-boost are 97.6%, 96.3% and 95.5% respectively at load current of 4A.

Sign in / Sign up

Export Citation Format

Share Document