A Novel Failure Analysis Technique for Semiconductor Packaging by Xenon Difluoride Gas

Author(s):  
Hongqing Zhang ◽  
Tom Wassick ◽  
Frank Pompeo
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.


Author(s):  
Sarven Ipek ◽  
David Grosjean

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.


Author(s):  
Kristopher D. Staller ◽  
Corey Goodrich

Abstract Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.


2020 ◽  
Vol 11 (1) ◽  
pp. 185
Author(s):  
Jian Shi ◽  
Mingbo Tong ◽  
Chuwei Zhou ◽  
Congjie Ye ◽  
Xindong Wang

The failure types and ultimate loads for eight carbon-epoxy laminate specimens with a central circular hole subjected to tensile load were tested experimentally and simulated using two different progressive failure analysis (PFA) methodologies. The first model used a lamina level modeling based on the Hashin criterion and the Camanho stiffness degradation theory to predict the damage of the fiber and matrix. The second model implemented a micromechanical analysis technique coined the generalized method of cells (GMC), where the 3D Tsai–Hill failure criterion was used to govern matrix failure, and the fiber failure was dictated by the maximum stress criterion. The progressive failure methodology was implemented using the UMAT subroutine within the ABAQUS/implicit solver. Results of load versus displacement and failure types from the two different models were compared against experimental data for the open hole laminates subjected to tensile displacement load. The results obtained from the numerical simulation and experiments showed good agreement. Failure paths and accurate damage contours for the tested specimens were also predicted.


Author(s):  
Steven B. Herschbein ◽  
Carmelo F. Scrudato ◽  
George K. Worth ◽  
Edward S. Hermann

Abstract The Focused Ion Beam (FIB) technique of internal modification for chip repair, layout verification, and internal signal probe access has become an integral part of the process for bringing advanced products to market. The pervasive switch from wire bond connections to single component flipchip solder bump mounting on high value products has greatly aided the task of FIB editing by placing the bare backside silicon of the die within easy reach. FIB chip circuit access begins with task-specific sample preparation. The package opening and silicon prep process is well defined and quite robust when full thickness chips are mounted to simple ceramic carriers. Unfortunately, the introduction of flexible organic laminate substrates and the development of stacked die packaging has further complicated the process. Multi-chip packages containing combinations of full thickness and thinned chips may be present. They could be wire-bond connected, or use Through-Silicon Vias (TSV) for double sided attachment. Multiple heat treatment cycles joining together materials with vastly different coefficients of thermal expansion (CTE) may result in severe package warpage and stress. All of these conditions and possible combinations have served to invalidate key elements of the established sample preparation process, and made each presented case unique. As the FIB team works to develop new precision techniques for internal circuitry access, the greater semiconductor packaging development and failure analysis community has benefited from the introduction of new tooling and methodologies.


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