The impact of device parameter variation on double gate tunneling FET and double gate MOSFET

Author(s):  
Lining Zhang ◽  
Mansun Chan ◽  
Frank He
2013 ◽  
Vol 685 ◽  
pp. 185-190
Author(s):  
Slimani Samia ◽  
Djellouli Bouaza

In spite of progress in silicon technology, the end of Mosfet scaling can be anticipated for the year 2015 so the introduction of high permittivity gate dielectric is the envisaged solution to reduce the current leakage that drives up power consumption. In this paper we investigate the impact of different gate length on SOI double gate MOSFET when SiO2 is replaced by ZrO2 as the gate dielectric using Nextnano Simulator. The impact of the quantum effects also observed on performance parameters of the DG-MOSFET such as on current, off current, drain induced barrier lowering, and sub-threshold. It is observed that less EOT with high permittivity reduces the tunnel current and serves to maintain high drive current.


2015 ◽  
Vol 36 ◽  
pp. 51-63 ◽  
Author(s):  
Vandana Kumari ◽  
Manoj Saxena ◽  
Mridula Gupta

This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.


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