Low Cost and High Density Packaging Technologies for Ultra Small IoT Computing Systems

2019 ◽  
Author(s):  
Hiroyuki Mori ◽  
Toyohiro Aoki ◽  
Eiji Nakamura ◽  
Akihiro Horibe ◽  
Kuniaki Sueoka ◽  
...  
Keyword(s):  
Low Cost ◽  
High Density ◽  
Computing Systems ◽  
High Density Packaging

scholarly journals High Density Packaging Technology

1981 ◽  
Vol 9 (1) ◽  
pp. 3-8
Author(s):  
Yusaku Nishi ◽  
Kazuo Mizuno
Keyword(s):  
Heat Sink ◽  
Large Scale ◽  
Low Cost ◽  
High Density ◽  
System Level ◽  
Back Side ◽  
Primary Yield ◽  
Chip Carrier ◽  
Multilayer Ceramic ◽  
High Density Packaging

A chip and wire, high density packaging approach has resulted in a low cost, large scale, high density, multi-chip package (MCP). The package includes 76 ICs, 1 resistor, and 34 capacitor chips on a 2 in × 3 in multilayer ceramic substrate (MLS) with 92 I/O leads. The package has a solder-sealed, metal cover over the chip-mount area, and a heat sink on the back side of the MLS.The primary yield was found to be around 70%. The rest was reworked with no significant labour. The software as well as hardware to minimize the test/rework labour would be a key to success in chip and wire MCPs. Also, efforts were made to reduce the material cost and the assembly labour. The thick film MLS was replaced by the ceramic MLS. The wire bonding was automated. Overall efforts reduced package cost to 1.25 times the conventional DIP-on-PCB counterpart (7.5 in × 9.1 in). Estimating its effectiveness at a system level, the reduction in the number of boards, connectors and cables would give MCPs an advantage over their counterparts. The improvement in reliability would be another advantageA comparison with other high density packaging technologies, chip carrier, and chip on tape, is also described.

Understanding and Optimizing Hybrid SSD with High-Density and Low-Cost Flash Memory

2021 ◽  
Author(s):  
Liang Shi ◽  
Longfei Luo ◽  
Yina Lv ◽  
Shicheng Li ◽  
Changlong Li ◽  
...  
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
High Density

Diagram of Electromigration Pattern in Eutectic Pb-Sn and Pb-Free Solders

2005 ◽  
Vol 297-300 ◽  
pp. 837-843
Author(s):  
Takashi Hasegawa ◽  
Masumi Saka
Keyword(s):  
Current Density ◽  
Solder Bump ◽  
High Density ◽  
Solder Bumps ◽  
Multi Phase ◽  
High Density Packaging

Solder is the most frequently used alloy, which serves as the bonding metal for electronics components. Recently, the interconnected bump is distinctly downsizing its bulk along with the integration of high-density packaging. The evaluation of electromigration damage for solder bumps is indispensable. Hence, it is fairly urgent to understand the mechanism of the electromigration damage to be capable of securing reliability of the solder bump and ultimately predicting its failure lifetime. Electromigration pattern in multi-phase material is determined by the combination of current density, temperature and current-applying time. In this paper, diagram of electromigration pattern (DEP) in solders is presented, where both of eutectic Pb-Sn and Pb-free solders are treated. DEP gives the basis for discussing and predicting the electromigration damage in solders.

Flipchip Bonding of Si Chip on Flexible PEN Foil using Novel Electronic 100 μm Pitch Fan-out Circuitry

2007 ◽  
Vol 1030 ◽  
Author(s):  
Jeroen van den Brand ◽  
Erik Veninga ◽  
Roel Kusters ◽  
Tomas Podprocky ◽  
Andreas Dietzel
Keyword(s):  
Thick Film ◽  
Low Cost ◽  
Cost Effective ◽  
High Density ◽  
Polyethylene Naphthalate ◽  
Electronic Circuitry ◽  
Effective Technology

AbstractA novel, cost effective technology to manufacture high density embedded electronic circuitry is demonstrated. The process consists of laser photoablation of the circuitry into a substrate through a mask and subsequent filling using a polymer thick film paste. Because the volume of the substrate is used it is possible to make thick and thereby highly conductive lines using low cost materials and processes. The process is demonstrated for a fan out circuitry in 100 µm thick polyethylene naphthalate (PEN). The fan out circuitry has linewidths of 50 µm and line spacings of 100 µm. The usability of the circuitry is demonstrated by the successful flipchip bonding of a thinned Si daisy chain dummy chip with 176 IO's.

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