Diagram of Electromigration Pattern in Eutectic Pb-Sn and Pb-Free Solders

2005 ◽  
Vol 297-300 ◽  
pp. 837-843
Author(s):  
Takashi Hasegawa ◽  
Masumi Saka
Keyword(s):  
Current Density ◽  
Solder Bump ◽  
High Density ◽  
Solder Bumps ◽  
Multi Phase ◽  
High Density Packaging

Solder is the most frequently used alloy, which serves as the bonding metal for electronics components. Recently, the interconnected bump is distinctly downsizing its bulk along with the integration of high-density packaging. The evaluation of electromigration damage for solder bumps is indispensable. Hence, it is fairly urgent to understand the mechanism of the electromigration damage to be capable of securing reliability of the solder bump and ultimately predicting its failure lifetime. Electromigration pattern in multi-phase material is determined by the combination of current density, temperature and current-applying time. In this paper, diagram of electromigration pattern (DEP) in solders is presented, where both of eutectic Pb-Sn and Pb-free solders are treated. DEP gives the basis for discussing and predicting the electromigration damage in solders.

Study of Void Formation Mechanism in Electroplated SnAg Solder Bump

2016 ◽  
Vol 2016 (1) ◽  
pp. 000638-000643
Author(s):  
Koji Tatsumi ◽  
Akio Sakai ◽  
Syunsuke Kawai ◽  
Takuma Katase ◽  
Takashi Miyazawa ◽  
...  
Keyword(s):  
Formation Mechanism ◽  
Electrolyte Solution ◽  
Current Density ◽  
Solder Bump ◽  
Cathode Surface ◽  
Void Formation ◽  
Gas Generation ◽  
Solder Bumps ◽  
Snag Solder ◽  
The Cross

Abstract SnAg electroplating method is widely used in the formation of LF solder bump for flip chip connection. While electroplating is able to form void free solder bump in a suitable operating condition, void may occur suddenly when used in mass production. This study aims at understanding the gas source in the void of electroplated SnAg solder bumps and determining the manufacturing process factors which affect the void formation. There are various types of void formation mode. One mode is H2 gas generation on cathode surface during electroplating. Both the cross-sections of solder bumps, as well as an analysis data of the gas in the void taken by the TDS (Thermal Desorption Spectrometry) were evaluated. The cross-section of the solder bump which contains void due to the reflow process revealed the existence of several tens of nm to several μm size pits in the solder bump before reflow. TDS analysis indicates that the pits consisted of mainly H2O, H2 and the decomposition of organics. A possible void formation mechanism is the evaporation of H2 gas and the incorporated electrolyte solution in the bump by reflow. These pits in the solder were caused by various process parameters. One of the causes is due to the setting of the current density in the SnAg electroplating process being inappropriate. The current density should be adjusted corresponding to the electrolyte performance and bump design such as PR thickness, opening diameter and bump density. The computer simulation demonstrated that a thick PR limits the diffusion of the Sn2+ ions into via holes and having the current density too high causes a lack of Sn2+ ions on the cathode surface and causes H2 gas generation. The other mode of void formation is Ag displacement of the under bump metallization (UBM) surface in dwell time in the SnAg electrolyte solution before the start of plating. The adjustment of each process parameter can eliminate the source of the void and achieve a high reliability of SnAg bump formation.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Effect of Bump Shape on Current Density and Temperature Distributions in Solder Bump Joints under Electromigration

2012 ◽  
Vol 569 ◽  
pp. 82-87
Author(s):  
Yi Li ◽  
Xiu Chen Zhao ◽  
Ying Liu ◽  
Hong Li
Keyword(s):  
Current Density ◽  
Solder Bump ◽  
Three Dimensional ◽  
Maximum Temperature ◽  
Time To Failure ◽  
Element Analysis ◽  
Temperature Distributions ◽  
Maximum Current ◽  
Mean Time ◽  
Waist Radius

Three dimensional thermo-electrical finite element analysis was employed to simulate the current density and temperature distributions for solder bump joints with different bump shapes. Mean-time-to-failure (MTTF) of electromigration was discussed. It was found that as the bump volume increased from hourglass bump to barrel bump, the maximum current density increased but the maximum temperature decreased. Hourglass bump with waist radius of 240 μm has the longest MTTF.

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