Predictive solder joint reliability assessment of board-on-chip package for DDR-II DRAM application

2005 ◽  
Author(s):  
Seungmin Cho ◽  
Changsoo Jang ◽  
Seongyoung Han ◽  
Jamil Ahmad ◽  
S.K. Sitaraman ◽  
...  
Keyword(s):  
Solder Joint ◽  
Reliability Assessment ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
On Chip

Reflow Process Simulation for Dispersion Evaluation of Solder Joint Shape on Chip Component

2009 ◽  
Author(s):  
Kanji Takagi ◽  
Qiang Yu ◽  
Tadahiro Shibutani ◽  
Hiroki Miyauchi
Keyword(s):  
Surface Tension ◽  
Solder Joint ◽  
High Reliability ◽  
Electronic Components ◽  
Reflow Process ◽  
Solder Joint Reliability ◽  
Automotive Electronic ◽  
Joint Reliability ◽  
On Chip ◽  
Joint Shape

The miniaturization and high reliability for automotive electronic components has been strongly requested. Generally, electronic component and printed wiring board are connected using solder joint. The reliability of solder joint has widely dispersion. For the dispersion reduction of solder joint reliability, not only design factors but manufacturing factors should be optimized. The evaluation of manufacturing factors for solder joint reliability was very difficult by experimental evaluation alone. Therefore, the reflow process simulation was established. The simulation was reenacted soldering process on chip component, which was the most severe reliability in automotive electronic components. The novelty of simulation was the coupled analysis of flow and rigid for simulating self-alignment of chip component. In this simulation, contact angle and surface tension was very important factor. So, these characteristics were measured based on Spread test and Wetting balance tests using the specimens. In the result, the solder joint shape of analysis was agree with the one of specimens using the measured contact angle and surface tension. Next, the effect of manufacturing process dispersion for solder joint shape was evaluated. The factors were mount offset and length unbalance of electrodes on chip component. As a result, the mount offset was not affected solder joint shape of chip component until a certain level. Also, the unbalance of electrode of chip component was not almost affected for solder joint shape of chip component because a part was moved to the center of part by surface tension of solder joint. Finally, the relation between the estimated solder joint shape and fatigue life of solder joints is evaluated using crack propagation analysis based on Manson-Coffin’s law and Miner’s rule. When the value of mount offset was large, the crack propagation mode was changed and the fatigue life of solder joint was decreased. As mentioned above, it was able to evaluate the relation between manufacturing factors and solder joint reliability. Accordingly, this simulation was very useful for consideration on the miniaturization, high reliability and appropriate margin for design of electronic components.

Solder Joint Reliability Assessment for a High Performance RF Ceramic Package

2014 ◽  
Vol 2014 (1) ◽  
pp. 000062-000067 ◽  
Author(s):  
Paul Charbonneau ◽  
Hans Ohman ◽  
Marc Fortin
Keyword(s):  
Solder Joint ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Unit Cost ◽  
Reliability Assessment ◽  
Lead Free ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Cte Mismatch ◽  
Life Predictions

The prediction of long term solder joint reliability, (SJR), of microelectronic devices and packaging solutions continues to challenge the microelectronic packaging industry, particularly with the introduction of lead-free materials, the push for higher performance (frequency/speed/thermal) and lower unit cost. High performance packages are generally custom designed and therefore have minimal industry data on configuration specific reliability performance. In this application, the package substrate coefficient of thermal expansion, (CTE), was closely matched to the die resulting in a relatively large CTE mismatch between the package and organic PCB. In addition, the package RF and thermal performance requirements required this particular solution to be configured as a “cavity down” perimeter ball array with a large central ground pad to electrically couple the package to the PCB. Given the package's unique design requirements and CTE mismatch, even modest daily temperature swings of 20°C usually found in a controlled or “Central Office” environment could have an adverse impact on the interconnect reliability. This study provides an overview of the solder joint reliability assessment methodologies performed for a custom design lead-free, high performance RF package as part of the requirements to demonstrate compliance to product specifications. SJR life predictions were made for varying package BGA configurations using a multi-tiered approach using constitutive material models, thermo-mechanical finite element simulations, and material specific fatigue models. Empirical accelerated life testing was performed and a life prediction obtained through modeling was validated. Finally, statistical failure distributions were fit to empirical data and discussed in the context of absolute solder life predictions of small fractions unit failures, (100ppm).

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