An analog front-end for remote sensor applications with high input common-mode rejection including a 16bit ΣΔ ADC in 0.35μm 3.3V CMOS process

2004 ◽  
Author(s):  
E. Compagne ◽  
S. Maulet ◽  
S. Genevey
Keyword(s):  
Cmos Process ◽  
High Input ◽  
Common Mode ◽  
Sensor Applications ◽  
Front End ◽  
Analog Front End ◽  
Remote Sensor

Low Distortion Analog Front-End for Digital Electret Microphone

2013 ◽  
Vol 475-476 ◽  
pp. 1633-1637
Author(s):  
Seung Yong Bae ◽  
Jong Do Lee ◽  
Eun Ju Choe ◽  
Gil Cho Ahn
Keyword(s):  
Audio Signal ◽  
Cmos Technology ◽  
Common Mode ◽  
Electret Microphone ◽  
Front End ◽  
Voltage Variation ◽  
Analog Front End ◽  
Source Follower ◽  
Source Voltage ◽  
Low Distortion

This paper presents a low distortion analog front-end (AFE) circuit to process electret microphone output signal. A source follower is employed for the input buffer to interface electret microphone directly to the IC with level shifting. A single-ended to differential converter with output common-mode control is presented to compensate the common-mode variation resulted from gate to source voltage variation in the source follower. A replica stage is adopted to control the output bias voltage of the single-ended to differential converter. The prototype AFE circuit fabricated in a 0.35μm CMOS technology achieves 68.2dB peak SNDR and 79.9dB SFDR over an audio signal bandwidth of 20kHz with 2.5V supply while consuming 1.05mW.

LOW POWER CONTINUOUS TIME COMMON MODE SENSING FOR COMMON MODE FEEDBACK CIRCUITS

2010 ◽  
Vol 19 (03) ◽  
pp. 519-528 ◽  
Author(s):  
M. PRAMOD ◽  
T. LAXMINIDHI
Keyword(s):  
Continuous Time ◽  
Input Impedance ◽  
Cmos Process ◽  
High Input ◽  
High Input Impedance ◽  
Common Mode ◽  
Standby Power ◽  
Low Distortion ◽  
Simulation Results ◽  
Feedback Circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.

scholarly journals 14.85 µW Analog Front-End for Photoplethysmography Acquisition with 142-dBΩ Gain and 64.2-pArms Noise

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 512
Author(s):  
Binghui Lin ◽  
Mohamed Atef ◽  
Guoxing Wang
Keyword(s):  
Dynamic Range ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Control Block ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback

2018 ◽  
Vol 53 (8) ◽  
pp. 2252-2262 ◽  
Author(s):  
Jinseok Lee ◽  
Geon-Hwi Lee ◽  
Hyojun Kim ◽  
SeongHwan Cho
Keyword(s):  
Positive Feedback ◽  
Input Impedance ◽  
High Input ◽  
High Input Impedance ◽  
Front End ◽  
Analog Front End

scholarly journals A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis

2018 ◽  
Vol 8 (3) ◽  
pp. 27 ◽  
Author(s):  
Avish Kosari ◽  
Jacob Breiholz ◽  
NingXi Liu ◽  
Benton Calhoun ◽  
David Wentzloff
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Noise ◽  
Signal Acquisition ◽  
Cmos Process ◽  
Ecg Signal ◽  
Ecg Monitoring ◽  
Power Circuit ◽  
Front End ◽  
Analog Front End

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications.

scholarly journals A Two Channel Analog Front end Design AFE Design with Continuous Time Σ-Δ Modulator for ECG Signal

2018 ◽  
Vol 8 (6) ◽  
pp. 5041 ◽  
Author(s):  
Mohammed Abdul Raheem ◽  
K Manjunathachari
Keyword(s):  
Frequency Response ◽  
Research Work ◽  
Cmos Process ◽  
Type I ◽  
Sigma Delta ◽  
Front End ◽  
Measured Frequency ◽  
Analog Front End ◽  
Measured Frequency Response ◽  
Power Application

In this context, the AFE with 2-channels is described, which has high impedance for low power application of bio-medical electrical activity. The challenge in obtaining accurate recordings of biomedical signals such as EEG/ECG to study the human body in research work. This paper is to propose Multi-Vt in AFE circuit design cascaded with CT modulator. The new architecture is anticipated with two dissimilar input signals filtered from 2-channel to one modulator. In this methodology, the amplifier is low powered multi-VT Analog Front-End which consumes less power by applying dual threshold voltage. Type -I category 2 channel signals of the first mode: 50 and 150 Hz amplified from AFE are given to 2nd CT sigma-delta ADC. Depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in a 0.18 um standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in 0.18 m standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, programmable gains from 52.6 dB to 72 dB, input referred noise of 3.5 μV in the amplifier bandwidth, NEF of 3.

scholarly journals A Demodulation Circuit For Analog Front End Of Passive Tag Chip

2021 ◽  
Vol 2065 (1) ◽  
pp. 012007
Author(s):  
Qinglong Li ◽  
Yong Xu ◽  
Qiao Li ◽  
Kun Peng ◽  
Xian Zhang
Keyword(s):  
Noise Suppression ◽  
Modulation Depth ◽  
Signal Frequency ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Passive Uhf Rfid ◽  
Average Value ◽  
Front End ◽  
Analog Front End ◽  
Detection Circuit

Abstract The demodulation circuit designed in this paper is suitable for the analog front end of passive UHF RFID tag chip, which can handle ASK signals with large changes in amplitude, modulation depth and signal frequency. Its performance meets the requirements of standards ISO/IEC 18000-6C and GB/T 29768-2013. Envelope detection circuit and limiter circuit are simple in structure and do not consume power. The comparison reference voltage is taken according to the average value of the envelope high and low levels, and is less affected by the dynamic changes of the input signal. Changing the width-to-length ratio of the MOSFETs in the feedback path of the comparator can adjust the hysteresis, with strong noise suppression and controllable sensitivity. The demodulator is implemented with TSMC 0.18 μm standard CMOS process. The simulation results show that the ASK signal modulation depth that the demodulator can handle is as low as 30%, and the maximum pulse width demodulation error is only 0.43%.

scholarly journals EMI Susceptibility Issue in Analog Front-End for Sensor Applications

2016 ◽  
Vol 2016 ◽  
pp. 1-9 ◽  
Author(s):  
Anna Richelli
Keyword(s):  
Analog Circuits ◽  
Crucial Role ◽  
Signal Acquisition ◽  
Sensor Signal ◽  
Sensory Signals ◽  
Sensor Applications ◽  
Front End ◽  
Analog Front End ◽  
Integrated Analog Circuits

The susceptibility to electromagnetic interferences of the analog circuits used in the sensor readout front-end is discussed. Analog circuits still play indeed a crucial role in sensor signal acquisition due to the analog nature of sensory signals. The effect of electromagnetic interferences has been simulated and measured in many commercial and integrated analog circuits; the main cause of the electromagnetic susceptibility is investigated and the guidelines to design high EMI immunity circuits are provided.

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