On the stability and throughput of compressive random access in MTC

Author(s):  
Jinho Choi
Keyword(s):  
2000 ◽  
Vol 619 ◽  
Author(s):  
Y. Gao ◽  
A.H. Mueller ◽  
E.A. Irene ◽  
O. Auciello ◽  
A.R. Krauss ◽  
...  

ABSTRACTAn in situ study of barrier layers using spectroscopic ellipsometry (SE) and Time-of-Flight (ToF) mass spectroscopy of recoiled ions (MSRI) is presented. First the formation of copper silicides has been observed by real-time SE and in situ MSRI in annealed Cu/Si samples. Second TaSiN films as barrier layers for copper interconnects were investigated. Failure of the TaSiN layers in Cu/TaSiN/Si samples was detected by real-time SE during annealing and confirmed by in situ MSRI. The effect of nitrogen concentration on TaSiN film performance as a barrier was also examined. The stability of both TiN and TaSiN films as barriers for electrodes for dynamic random access memory (DRAM) devices has been studied. It is shown that a combination of in situ SE and MSRI can be used to monitor the evolution of barrier layers and detect the failure of barriers in real-time.


Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 611 ◽  
Author(s):  
Ik Joon Chang ◽  
Yesung Kang ◽  
Youngmin Kim

Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM.


Energies ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 1017 ◽  
Author(s):  
Linlin Tan ◽  
Ming Zhang ◽  
Songcen Wang ◽  
Shulei Pan ◽  
Zhenxing Zhang ◽  
...  

As is common in multi-load wireless power transfer (WPT) systems based on series–series compensation topology, the power received by loads and the efficiency of the process are highly sensitive to changes in the number of loads. To guarantee that the power supplied to a load remains stable when other loads access or leave the system, we propose an improved multi-load system for WPT. The new system uses an LCC/S topology (based on inductor–capacitor–inductor or LCL topology) to keep the power received by the loads stable. By comparing two scenarios (ideal and real models based on LCC/S topology), we aim to eliminate cross-coupling between receiving coils by connecting compensating capacitors in series on the receiving side. In this way, the stability of the power received by loads is further improved. Moreover, a method of optimizing control over the efficiency is proposed based on the effect on the overall efficiency of impedance and number of loads. This allows us to optimize the overall efficiency of the system. Finally, a system to verify our theoretical analysis is established and used to show the validity and effectiveness of the proposed system.


2000 ◽  
Vol 655 ◽  
Author(s):  
K.L. Saenger ◽  
P.C. Andricacos ◽  
S.D. Athavale ◽  
J.D. Baniecki ◽  
C. Cabral ◽  
...  

AbstractMaterials requirements for electrodes and barriers in high density dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) are reviewed, and some approaches to barrier materials and device geometries are described. Electrode/barrier topics covered in more detail include Pt reactivity with Si-containing barriers and dielectric overlayers, the application of a Bragg-Brentano x-ray diffraction technique to quantitatively probe Pt and Ir electrode morphology and thickness changes during ferroelectric processing, the stability of metal oxide electrode materials in reducing ambients, electrode patterning techniques (including Pt electroplating), and electrical properties of 3-D capacitors in 256k arrays as a function of top electrode annealing treatments.


1994 ◽  
Vol 26 (02) ◽  
pp. 498-515 ◽  
Author(s):  
Wojciech Szpankowski

We consider the standard slotted ALOHA system with a finite number of buffered users. Stability analysis of such a system was initiated by Tsybakov and Mikhailov (1979). Since then several bounds on the stability region have been established; however, the exact stability region is known only for the symmetric system and two-user ALOHA. This paper proves necessary and sufficient conditions for stability of the ALOHA system. We accomplish this by means of a novel technique based on three simple observations: applying mathematical induction to a smaller copy of the system, isolating a single queue for which Loynes' stability criteria is adopted, and finally using stochastic dominance to verify the required stationarity assumptions in the Loynes criterion. We also point out that our technique can be used to assess stability regions for other multidimensional systems. We illustrate it by deriving stability regions for buffered systems with conflict resolution algorithms (see also Georgiadis and Szpankowski (1992) for similar approach applied to stability of token-passing rings).


2016 ◽  
Vol 64 (7) ◽  
pp. 2985-2998 ◽  
Author(s):  
Yi Zhong ◽  
Martin Haenggi ◽  
Tony Q. S. Quek ◽  
Wenyi Zhang

2010 ◽  
Vol 1251 ◽  
Author(s):  
Yu-Jen Huang ◽  
Min-Chuan Tsai ◽  
Chiung-Hsin Wang ◽  
Tsung-Eong Hsieh

AbstractA study on microstructure and electrical property of cerium (Ce)-doped Ge2Sb2Te5 (GST) layers for phase-change memory (PCM) application were presented. Ce doping does not suppress the resistivity of amorphous GST and the resistivity ratio of amorphous and crystalline GST remains at about 105. Further, Ce-doping escalates the recrystallization temperature (Tx) of GST from 159 to 236°C. Such a unique behavior would greatly benefit the preservation of signal contrast as well as the high-density signal storage and will not cause the increase of device writing current. X-ray diffraction (XRD) indicated that Ce doping stabilizes amorphous GST and suppresses the formation of hexagonal phase. Transmission electron microscopy (TEM) revealed Ce doping refines the grain size of GST. Kissinger's analysis found that Tx and activation energy (Ea) of phase transition for doped-GST both increase with the increase of Ce content. Isothermal experiment found the Ce doping increases temperature for 10-yr data retention from 76 and 170°C. This is attributed to the presence of Ce solutes in GST matrix that inhibits the grain growth during recrystallization.Static-mode electrical test on PCM device containing doped GST as the programming layer found that Ce incorporation indeed increases the switching threshold voltage (Vth). This confirmed that Ce doping effectively retards the crystallization of GST and improves the stability of amorphous GST.


2017 ◽  
Vol 26 (03) ◽  
pp. 1740009 ◽  
Author(s):  
Bander Saman ◽  
P. Gogna ◽  
El-Sayed Hasaneen ◽  
J. Chandy ◽  
E. Heller ◽  
...  

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.


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