scholarly journals Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 611 ◽  
Author(s):  
Ik Joon Chang ◽  
Yesung Kang ◽  
Youngmin Kim
Keyword(s):  
Threshold Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Channel Length ◽  
Voltage Level ◽  
Exact Data ◽  
Optimum Energy ◽  
The Stability ◽  
20 Nm ◽  
Near Threshold

Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM.

scholarly journals Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

2020 ◽  
Vol 10 (2) ◽  
pp. 16
Author(s):  
Sriram Vangal ◽  
Somnath Paul ◽  
Steven Hsu ◽  
Amit Agarwal ◽  
Ram Krishnamurthy ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Energy Budgets ◽  
Voltage Range ◽  
Ip Blocks ◽  
Test Chips ◽  
Many Core ◽  
Near Threshold ◽  
Design Techniques

Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law.

ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE

2013 ◽  
Vol 22 (06) ◽  
pp. 1350048 ◽  
Author(s):  
SARAVANAN RAMAMOORTHY ◽  
HAIBO WANG
Keyword(s):  
Memory Effect ◽  
Threshold Voltage ◽  
Power Supply ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Design Modification ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Near Threshold

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

LEAKAGE POWER REDUCTION IN SRAM AT NANOSCALE

2011 ◽  
Vol 10 (04n05) ◽  
pp. 755-759
Author(s):  
K. SUNIL KUMAR
Keyword(s):  
Supply Voltage ◽  
Channel Length ◽  
Gate Leakage ◽  
Leakage Currents ◽  
Voltage Level ◽  
Node Potential ◽  
Sram Cell ◽  
Effective Voltage ◽  
The One ◽  
The Impact

In this work the impact of gate leakage on SRAM is described and two approaches for reducing gate leakage currents are examined in detail. In one approach, the supply voltage is reduced while in the other the potential of the ground node is raised. In both the approaches the effective voltage across SRAM cell is reduced in inactive mode using a dynamic self-controllable switch. Simulation results based on BPTM (Berkeley Predictive Technology Model) for 45 nm channel length device show that the scheme in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node potential is raised. Results obtained show that 96% reduction in the leakage currents of SRAM can be achieved.

scholarly journals Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 685
Author(s):  
Ming-Hwa Sheu ◽  
S M Salahuddin Morsalin ◽  
Chang-Ming Tsai ◽  
Cheng-Jie Yang ◽  
Shih-Chang Hsia ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Average Energy ◽  
Process Technology ◽  
Charge Voltage ◽  
Low Voltage Operation ◽  
Noise Margin ◽  
Sram Design ◽  
Near Threshold

To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged and NLBL scheme being operated by the write bit-line column to work out for the write half-select condition. The proposed local bit-line SRAM design reduces variations and enhances the read stability, the write capacity, prevents the bit-line leakage current, and the designed pre-charged circuit has achieved an optimal pre-charge voltage during the near-threshold operation. Compared to the conventional 6 T SRAM design, the optimal pre-charge voltage has been improved up to 15% for the read static noise margin (RSNM) and the write delay enriched up to 22% for the proposed NLBL SRAM design which is energy-efficient. At 400 mV supply voltage and 25 MHz operating frequency, the read and write energy consumption is 0.22 pJ and 0.23 pJ respectively. After comparing with the related works, the access average energy (AAE) is lower than in other works. The overall performance for the proposed local bit-line SRAM has achieved the highest figure of merit (FoM). The designed architecture has been implemented based on the 1-Kb SRAM macros and TSMC−40 nm GP process technology.

Dependence of Current Harmonics of Greenhouse Irradiators on Supply Voltage

2020 ◽  
pp. 85-88 ◽  
Author(s):  
Nadezhda P. Kondratieva
Keyword(s):  
Mathematical Models ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Feasibility Studies ◽  
Power Losses ◽  
Voltage Level ◽  
Supply Networks ◽  
Current Harmonics ◽  
Cable Lines ◽  
Harmonic Composition

The article describes the results of the study concerning the effect of the voltage level on current harmonic composition in greenhouses irradiators. It is found that its change affects the level of current harmonics of all types of the studied greenhouse irradiators. With decrease of nominal supply voltage by 10 %, the total harmonic distortion THDi decreases by 9 % for emitters equipped with high pressure sodium lamps (HPSL), by 10 % for emitters with electrode-less lamps and by 3 % for LED based emitters. With increase of nominal supply voltage by 10 %, THDi increases by 23 % for lighting devices equipped with HPSL, by 10 % for irradiators with electrode-less lamps and by 3 % for LED based emitters. Therefore, changes of supply voltage cause the least effect on the level of current harmonics of LED based emitters and then the emitters with electrode-less lamps. Change of the level of supply voltage causes the greatest effect on the level of current harmonics of HPSL based irradiators. Mathematical models of dependence of THDi on the level of supply voltage for greenhouse emitters equipped with LED, electrode-less lamps and HPSL lamps were formulated. These mathematical models may be used for calculations of total current when selecting transformers and supply cable lines for greenhouse lighting devices, for design of new or reconstruction of existing irradiation systems of greenhouse facilities, and for calculation of power losses in power supply networks of greenhouse facilities during feasibility studies for energy saving and energy efficiency increasing projects.

Comparative Assessment of Optical Techniques for Semi-Invasive SRAM Data Read-out on an MSP430 Microcontroller

2018 ◽  
Author(s):  
Tuba Kiyan ◽  
Heiko Lohrke ◽  
Christian Boit
Keyword(s):  
Supply Voltage ◽  
Photon Emission ◽  
Random Access ◽  
Integration Time ◽  
Security Evaluation ◽  
Testing And Debugging ◽  
Advantages And Disadvantages ◽  
The Core ◽  
Voltage Signal ◽  
Chip Testing

Abstract This paper compares the three major semi-invasive optical approaches, Photon Emission (PE), Thermal Laser Stimulation (TLS) and Electro-Optical Frequency Mapping (EOFM) for contactless static random access memory (SRAM) content read-out on a commercial microcontroller. Advantages and disadvantages of these techniques are evaluated by applying those techniques on a 1 KB SRAM in an MSP430 microcontroller. It is demonstrated that successful read out depends strongly on the core voltage parameters for each technique. For PE, better SNR and shorter integration time are to be achieved by using the highest nominal core voltage. In TLS measurements, the core voltage needs to be externally applied via a current amplifier with a bias voltage slightly above nominal. EOFM can use nominal core voltages again; however, a modulation needs to be applied. The amplitude of the modulated supply voltage signal has a strong effect on the quality of the signal. Semi-invasive read out of the memory content is necessary in order to remotely understand the organization of memory, which finds applications in hardware and software security evaluation, reverse engineering, defect localization, failure analysis, chip testing and debugging.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Effect of Varying Memory Device Architectures on the Electrical Properties of P(VDF/TrFE)(72/28) Copolymer Thin Film

2008 ◽  
Vol 54 ◽  
pp. 491-496 ◽  
Author(s):  
Chang Woo Choi ◽  
Arun Anand Prabu ◽  
Sun Yoon ◽  
Yu Min Kim ◽  
Kap Jin Kim
Keyword(s):  
Vinylidene Fluoride ◽  
Field Effect Transistors ◽  
Random Access ◽  
Drain Current ◽  
Random Copolymer ◽  
Memory Device ◽  
Channel Length ◽  
Memory Retention ◽  
Voltage Measurement ◽  
Electrical Measurements

In this study, the dipole switching and non-volatile memory functionality of poly(vinylidene fluoride-trifluoroethylene) (PVDF/TrFE)(72/28 mol%) random copolymer ultrathin films were analyzed. PVDF/TrFE(72/28) used as ferroelectric insulator in varying memory device architectures such as metal-ferroelectric polymer-metal (MFM), MF-insulator-semiconductor (MFIS), MIS and ferroelectric field-effect transistors (FeFET) were examined using different electrical measurements. A maximum data writing speed of 1.69 MHz was calculated from the switching time measured using MFM architecture. Compared to MFM, MFIS device architecture was found to be more suitable for distinguishing the ‘0’ and ‘1’ state using the capacitance-voltage measurement. With FeFET, the measured drain current (Id) as well as its memory window increased with decreasing channel length, thereby enabling the easier identification of ‘0’ and ‘1’ state comparable to the MFIS case. The data obtained from this study will be useful in the fabrication of non-volatile random access memory (NVRAM) devices operating at lower voltage with faster data R/W/E speed and memory retention capability.

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