A compact, low power, fully integrated clock frequency doubler

Author(s):  
A. Tajalli ◽  
A. Khodaverdi ◽  
S.M. Atarodi
2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.


2020 ◽  
Vol 2 ◽  
pp. 98-102
Author(s):  
Wing-Kong Ng ◽  
Wing-Shan Tam ◽  
Chi-Wah Kok

2002 ◽  
Author(s):  
Ronald E. Reedy ◽  
Hal Anthony ◽  
Charles Kuznia ◽  
Mike Pendelton ◽  
Jim Cable ◽  
...  

2014 ◽  
Vol 49 (8) ◽  
pp. 1682-1693 ◽  
Author(s):  
Seokhyeon Jeong ◽  
Zhiyoong Foo ◽  
Yoonmyung Lee ◽  
Jae-Yoon Sim ◽  
David Blaauw ◽  
...  

1998 ◽  
Vol 45 (4) ◽  
pp. 2272-2278 ◽  
Author(s):  
J. Vandenbussche ◽  
F. Leyn ◽  
G. Van der Plas ◽  
G. Gielen ◽  
W. Sansen

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