Failure Localization Method in Open Mode Failure Analysis of Advanced Package

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

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Process Induced Defects in the Silicon Substrate: Approaches for Successful Failure Analysis

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0092 ◽

2010 ◽

Author(s):

J.G. van Hassel ◽

Xiao-Mei Zhang

Keyword(s):

Failure Analysis ◽

Case Studies ◽

Silicon Substrate ◽

Processing Technique ◽

Electrical Characteristics ◽

Localization Method ◽

The Right ◽

Induced Defects

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

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Comparison of Active and Passive Voltage Contrast for Failure Localization

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0331 ◽

2007 ◽

Author(s):

R. Rosenkranz ◽

W. Werner

Keyword(s):

Case Studies ◽

Optical Beam ◽

Leakage Currents ◽

Localization Method ◽

Voltage Contrast ◽

Failure Localization

Abstract In many cases of failure localization, passive voltage contrast (PVC) localization method does not work, because it is not possible to charge up conducting structures which supposed to be dark in the SEM and FIB images. The reason for this is leakage currents. In this article, the authors show how they succeeded in overcoming these difficulties by the application of the active voltage contrast (AVC) method as it was described as biased voltage contrast by Campbell and Soden. They identified three main cases where the PVC didn't work but where they succeeded in failure localization with the AVC method. This is illustrated with the use of two case studies. Compared to the optical beam based methods the resolution is much better so a single failing contact of e.g. 70 nm technology can clearly be identified which cannot be done by TIVA or OBIRCH.

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SRAM Failure Analysis Strategy

ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2003p0177 ◽

2003 ◽

Author(s):

P. Egger ◽

C. Burmer

Keyword(s):

Liquid Crystal ◽

Failure Analysis ◽

The Other ◽

Other Hand ◽

Analysis Strategy ◽

Emission Microscopy ◽

Metal Layers ◽

Failure Localization

Abstract The area of embedded SRAMs in advanced logic ICs is increasing more and more. On the other hand smaller structure sizes and an increasing number of metal layers make conventional failure localization by using emission microscopy or liquid crystal inefficient. In this paper a SRAM failure analysis strategy will be presented independent on layout and technology.

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An integrated framework for mode failure analysis, delay time model and multi-criteria decision-making for determination of inspection intervals in complex systems

Journal of Loss Prevention in the Process Industries ◽

10.1016/j.jlp.2017.10.013 ◽

2018 ◽

Vol 51 ◽

pp. 17-28 ◽

Cited By ~ 5

Author(s):

Julianna Gomes da Silva ◽

Rodrigo Sampaio Lopes

Keyword(s):

Decision Making ◽

Complex Systems ◽

Failure Analysis ◽

Delay Time ◽

Multi Criteria Decision Making ◽

Time Model ◽

Integrated Framework ◽

Mode Failure

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Common mode failure analysis

IEEE Transactions on Power Apparatus and Systems ◽

10.1109/t-pas.1975.31820 ◽

1975 ◽

Vol 94 (1) ◽

pp. 27-30 ◽

Cited By ~ 32

Author(s):

W.C. Gangloff

Keyword(s):

Failure Analysis ◽

Common Mode ◽

Mode Failure

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Best test pattern failure analysis flow for functional logic failure localization by IR-OBIRCH technique

2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2009.5232672 ◽

2009 ◽

Cited By ~ 1

Author(s):

A. Machouat ◽

G. Haller ◽

V. Goubier ◽

D. Lewis ◽

P. Perdu ◽

...

Keyword(s):

Failure Analysis ◽

Test Pattern ◽

Functional Logic ◽

Failure Localization

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Scanning Capacitance Microscopy Application for Bipolar and CMOS Doping Issues in Semiconductor Failure Analysis

ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2005p0307 ◽

2005 ◽

Author(s):

Coswin Lin ◽

Homy Ou ◽

Chia-Hsing Chao ◽

Shey-Shi Lu

Keyword(s):

Failure Analysis ◽

Failure Mechanism ◽

Cross Section ◽

Layer By Layer ◽

Localization Method ◽

Scanning Capacitance Microscopy ◽

Leakage Path ◽

Schematic Cross Section ◽

Power Leakage ◽

Plane View

Abstract Scanning Capacitance Microscopy (SCM) has been extensively used for identifying doping issues in semiconductor failure analysis. In this paper, the root causes of two recent problems -- bipolar beta loss and CMOS power leakage -- were verified using SCM images. Another localization method, layer-by-layer circuit repair with IROBIRCH detection, was also utilized to locate possible defects. The resulting failure mechanism for bipolar beta loss is illustrated with a schematic cross section, which shows the leakage path from the emitter to the base. In the case of CMOS power leakage, the abnormal implantation of the Pwell region was identified with the Plane view SCM image.

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